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never stop thinking. HYB18T512161BF-20/22/25/28/33 512-mbit x16 ddr2 sdram rohs compliant data sheet, rev. 1.31, mar. 2006 memory products
edition 2006-03 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2006. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. under no circumstances may the infineon technologies produ ct as referred to in this data sheet be used in 1. any applications that are inte nded for military usage (including but not limited to weaponry), or 2. any applications, devices or systems which are safety cr itical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "critical systems"), if a) a failure of the infineon technologies product can re asonable be expected to - directly or indirectly - (i) have a detrimental effect on such critical systems in terms of reli ability, effectivenes s or safety; or (ii) cause the failure of such critical systems; or b) a failure or malfunction of such cr itical systems can reaso nably be expected to - directly or indirectly - (i) endanger the health or the life of the user of such critical systems or any other person; or (ii) otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible).
template: mp_a4_s_rev321 / 3 / 2005-10-05 hyb18t512161bf revision history: 2006-03 , rev. 1.31 page subjects (major cha nges since last revision) 9 added power supply info for [-20 and -22] 86 table 41: change idd max to idd typ 77 - 80 corrected ac timing values for -20 speedsort in table 35 and table 36 previous revision: rev. 1.21, 2006-02 67 table 18: added speed sort -20 71 table 24: added speed sort -20 76 table 33 and table 34: added speed sort -20 77 table 35: change cl=7 2.0 t ck (speed sort -20) 78 table 36: added all values for speed sort -20 86 table 41: added all i dd values (all speed sorts) we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send us your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram data sheet 4 rev. 1.31, 2006-03 05102005-c5u8-7tle 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 pin configuration and block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 512 mbit ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 basic functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 power on and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 programming the mode register and extended mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 ddr2 sdram mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 ddr2 sdram extended mode register set emr(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 dll enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 output disable (qoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9 single-ended and differential data strobe signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 extended mode register emr(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11 extended mode register emr(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 off-chip driver (ocd) impedance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.13 on-die termination (odt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.14 bank activate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.15 read and write commands and access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 3.16 posted cas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.17 burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.18 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.19 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.20 write data mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.21 burst interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.22 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.22.1 read followed by a precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.22.2 write followed by precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.23 auto-precharge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.23.1 read with auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.23.2 write with auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.23.3 read or write to precharge command spacing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.23.4 concurrent auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.24 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.24.1 auto-refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.24.2 self-refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.25 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.26 other commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.26.1 no operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.26.2 deselect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.27 input clock frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.28 asynchronous cke low reset event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.29 dll off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.29.1 dll off frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table of contents
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram data sheet 5 rev. 1.31, 2006-03 05102005-c5u8-7tle 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3 dc & ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.4 output buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.5 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.6 overshoot and undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.7 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.7.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.7.2 ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.7.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6 specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.1 i dd test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.1.1 on die termination (odt) current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.1 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.2 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table of contents
data sheet 6 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram list of figures figure 1 pin configuration for 16 components, p-tfbga-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2 block diagram 8 mbit 16 i/o 4 internal memory banks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4 initialization sequence after power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5 ocd impedance adjustment flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 6 timing diagram adjust mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7 timing diagram drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 8 functional representation of odt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 9 odt timing for active and standby (idle) modes (synchronous odt timings). . . . . . . . . . . . . . . 31 figure 10 odt timing for precharge power-down and active power-down mode. . . . . . . . . . . . . . . . . . . . 32 figure 11 odt mode entry timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12 odt mode exit timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13 bank activate command cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14 read timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15 activate to read timing exampl e: read followed by a write to the same bank . . . . . . . . . . . . . . 37 figure 16 read to write timing example: read followed by a wr ite to the same bank . . . . . . . . . . . . . . . . 37 figure 17 read to write timing example: read followed by a wr ite to the same bank . . . . . . . . . . . . . . . . 38 figure 18 read to write timing example: read followed by a wr ite to the same bank . . . . . . . . . . . . . . . . 38 figure 19 write to read timing example: write followed by a read to the same bank . . . . . . . . . . . . . . . . . 38 figure 20 basic read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 21 read operation example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 22 read operation example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 23 read followed by write example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 24 seamless read operation example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 25 seamless read operation example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 26 basic write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 27 write operation example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 28 write operation example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 29 write followed by read example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 30 seamless write operation example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 31 seamless write operation example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 32 write data mask timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 33 write operation with data mask example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 34 read interrupt timing example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 35 write interrupt timing example 2 cl = 3, al = 0, wl = 2, bl = 8 . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 36 read operation followed by precharge ex ample 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 37 read operation followed by precharge ex ample 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 38 read operation followed by precharge ex ample 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 39 read operation followed by precharge ex ample 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 40 read operation followed by precharge ex ample 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 41 write followed by precharge example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 42 write followed by precharge example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 43 read with auto-precharge example 1, fo llowed by an activation to the same bank ( t rc limit) . . 53 figure 44 read with auto-precharge example 2, fo llowed by an activation to the same bank ( t ras limit) . 53 figure 45 read with auto-precharge example 3, followed by an activation to the same bank . . . . . . . . . . 54 figure 46 read with auto-precharge example 4, followed by an activation to the same bank, . . . . . . . . . . 54 figure 47 write with auto-precharge example 1 ( t rc limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 48 write with auto-precharge example 2 (wr + t rp limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 49 auto refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 list of figures
data sheet 7 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram list of figures figure 50 self refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 51 active power-down mode entry and exit after an activate command . . . . . . . . . . . . . . . . . . . . . 60 figure 52 active power-down mode entry and exit example after a read command rl = 4 (al = 1, cl =3), bl = 4 61 figure 53 active power-down mode entry and exit example after a write command wl = 2, t wtr =2,bl= 4 61 figure 54 active power-down mode entry and exit example after a write command with ap wl = 2, wr = 3, bl = 4 62 figure 55 precharge power down mode entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 56 auto-refresh command to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 57 mrs, emrs command to power-down en try . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 figure 58 input frequency change exampl e during precharge power-down mode . . . . . . . . . . . . . . . . . . . 64 figure 59 asynchronous low reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 60 single-ended ac input test conditio ns diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 61 differential dc and ac input and output logic levels diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 62 ac overshoot / undershoot diagram for address and co ntrol pins . . . . . . . . . . . . . . . . . . . . . . . 75 figure 63 ac overshoot / undershoot diagram for clock, data , strobe and mask pins . . . . . . . . . . . . . . . . 75 figure 64 package outline p-tfbga-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
data sheet 8 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram list of tables table 1 ordering information for rohs compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2 pin configuration of ddr sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5 512-mbit ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6 mode register definition (ba[2:0] = 000b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7 extended mode register definition ( ba[2:0] = 001b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8 single-ended and differential data strobe signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9 emrs(2) programming extended mode register definition (ba[2:0]=010 b ) . . . . . . . . . . . . . . . . . 25 table 10 emr(3) programming extended mode register definition (ba[2:0]=010 b ) . . . . . . . . . . . . . . . . . . 26 table 11 off chip driver program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12 off-chip-driver adjust program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13 odt truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14 burst length and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 15 bank selection for precharge by addr ess bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 16 minimum command delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 17 command delay table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 18 dll off frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 19 command truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 20 clock enable (cke) truth table for synchronous transiti ons . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 21 data mask (dm) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 22 dram component operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 23 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 24 recommended dc operating conditions (sstl_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 25 odt dc electrical charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 26 input and output leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 27 dc & ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 28 single-ended ac input test conditio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 29 differential dc and ac input and output logic levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 30 full strength calibrated pull-up driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 31 full strength calibrated pu ll-down driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 32 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 33 ac overshoot / undershoot specification for address and control pins . . . . . . . . . . . . . . . . . . . . 75 table 34 ac overshoot / undershoot spec ification for clock, data, strobe and mask pins . . . . . . . . . . . . 75 table 35 speed grade definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 36 timing parameter by speed grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 37 timing parameter by speed grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 38 odt ac electrical characteristics and operating condi tions for all bins. . . . . . . . . . . . . . . . . . . . 83 table 39 i dd measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 40 definition for i dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 41 i dd specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 42 i dd measurement test condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 43 odt current per terminated input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 44 package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 list of tables
data sheet 9 rev. 1.31, 2006-03 05102005-c5u8-7tle 512-mbit x16 ddr2 sdram ddr2 sdram hyb18t512161bf 1overview this chapter gives an overview of the 512-mbit double -data-rate-two sdram product family and describes its main characteristics. 1.1 features the 512-mbit double-data-rate-two sdra m offers the following key features: ? 1.8 v 0.1v v dd for [?25/?28/?33] 2.0 v 0.1v v dd for [?20/?22] 1.8 v 0.1v v ddq for [?25/?28/?33] 2.0 v 0.1v v ddq for [?20/?22] ? dram organizations with 16 data in/outputs ? double data rate architec ture: two data transfers per clock cycle four internal banks for concurrent operation ? programmable cas latency: 3, 4, 5, 6, 7 ? programmable burst length: 4 and 8 ? differential clock inputs (ck and ck ) ? bi-directional, differential data strobes (dqs and dqs ) are transmitted / rece ived with data. edge aligned with read data and center-aligned with write data. ? dll aligns dq and dqs transitions with clock ?dqs can be disabled for single-ended data strobe operation ? commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs ? data masks (dm) for write data ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance adjustment (ocd) and on-die-termination (odt) for better signal quality. ? auto-precharge operation for read and write bursts ? auto-refresh, self-ref resh and power saving power-down modes ? average refresh period 7.8 s at a t case lower than 85 c, 3.9 s between 85 c and 95 c ? full strength and reduced strength (60%) data- output drivers ? 2kb page size ? packages: p-tfbga-84 for 16 components ? rohs compliant products 1) 1) rohs compliant product: restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2 002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercury, lead, cadmiu m, hexavalent chromium, po lybrominated biphenyls and polybrominated biphenyl ethers. table 1 ordering information for rohs compliant products product number org. clock (mhz) package hyb18t512161bf?20/22/25/28/33 16 500/450/400/350/300 p-tfbga-84
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram overview data sheet 10 rev. 1.31, 2006-03 05102005-c5u8-7tle 1.2 description the 512-mb ddr2 dram is a high-speed double- data-rate-two cmos dram device containing 536,870,912 bits and internally configured as a quad- bank dram. the 512-mb device is organized as 8mbit 16 i/o 4 banks chip. these devices achieve high speed transfer rates starting at 400 mb/sec/pin for general applications. the device is designed to comply with all ddr2 dram key features: 1. posted cas with additive latency, 2. write latency = read latency - 1, 3. normal and weak strength data-output driver, 4. off-chip driver (ocd ) impedance adjustment 5. on-die termination (odt) function. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential dqs-dqs pair in a source synchronous fashion. a 15-bit address bus for 16 components is used to convey row, column and bank address information in a ras -cas multiplexing style. an auto-refresh and self-refresh mode is provided along with various power-saving power-down modes. the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. the ddr2 sdram is available in p-tfbga package. note: for product nomenclature see chapter 8 of this data sheet
data sheet 11 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram pin configuration and block diagrams 2 pin configuration and block diagrams 2.1 pin configuration the pin configuration of a ddr2 sdram is listed by function in table 2 . the abbreviations used in the pin#/buffer type columns are explained in table 3 and table 4 respectively. the pin numbering for the fbga package is depicted in figure 1 for 4, figure 2 for 8 and figure 3 for 16 . table 2 pin configuration of ddr sdram ball#/pin# name pin type buffer type function clock signals 16 organization j8 ck i sstl clock signal ck, complementary clock signal ck k8 ck isstl k2 cke i sstl clock enable control signals 16 organization k7 ras isstl row address strobe (ras), column address strobe (cas), write enable (we) l7 cas isstl k3 we isstl l8 cs isstl chip select address signals 16 organization l2 ba0 i sstl bank address bus 1:0 l3 ba1 i sstl l1 nc ? ? m8 a0 i sstl address signal 12:0,address signal 10/autoprecharge m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram pin configuration and block diagrams data sheet 12 rev. 1.31, 2006-03 05102005-c5u8-7tle data signals 16 organization g8 dq0 i/o sstl data signal 15:0 note: bi-directional data bus. dq[15:0] for 16 components g2 dq1 i/o sstl h7 dq2 i/o sstl h3 dq3 i/o sstl h1 dq4 i/o sstl h9 dq5 i/o sstl f1 dq6 i/o sstl f9 dq7 i/o sstl c8 dq8 i/o sstl c2 dq9 i/o sstl d7 dq10 i/o sstl d3 dq11 i/o sstl d1 dq12 i/o sstl d9 dq13 i/o sstl b1 dq14 i/o sstl b9 dq15 i/o sstl data strobe 16 organization b7 udqs i/o sstl data strobe upper byte a8 udqs i/o sstl f7 ldqs i/o sstl data strobe lower byte e8 ldqs i/o sstl data mask 16 organization b3 udm i sstl data mask upper byte f3 ldm i sstl data mask lower byte power supplies 16 organizations a9,c1,c3,c7, c9 v ddq pwr ? i/o driver power supply a1 v dd pwr ? power supply a7,b2,b8,d2, d8 v ssq pwr ? power supply a3,e3 v ss pwr ? power supply power supplies 16 organization j2 v ref ai ? i/o reference voltage e9, g1, g3, g7, g9 v ddq pwr ? i/o driver power supply j1 v ddl pwr ? power supply e1, j9, m9, r1 v dd pwr ? power supply table 2 pin configuration of ddr sdram ball#/pin# name pin type buffer type function
data sheet 13 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram pin configuration and block diagrams e7, f2, f8, h2, h8 v ssq pwr ? power supply j7 v ssdl pwr ? power supply j3,n1,p9 v ss pwr ? power supply not connected 16 organization a2, e2, l1, r3, r7, r8 nc nc ? not connected other pins 16 organization k9 odt i sstl on-die termina tion control table 3 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 4 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 op erational states, active low and tristate, and allows multiple devices to share as a wire-or. table 2 pin configuration of ddr sdram ball#/pin# name pin type buffer type function
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram pin configuration and block diagrams data sheet 14 rev. 1.31, 2006-03 05102005-c5u8-7tle figure 1 pin configuration for 16 components, p-tfbga-84 (top view) note: 1. udqs/udqs is data strobe for dq[15:8], ldqs/ldqs is data strobe for dq[7:0] 2. ldm is the data mask signal for dq[7:0], udm is the data mask signal for dq[15:8] 3. v ddl and v ddsl are power and ground for the dll. they are isolated on the device from v dd , v ddq , v ss and v ssq. - 0 0 4 6 $ $ . # ! 6 3 3 1 .# 6 3 3 # + % # + 6 3 3 5 $ - $ 1 6 $ $ 1 $ 1 $ 1 6 3 3 6 $ $ , ! 6 3 3 1 $ 1 , $ 1 3 2 ! 3 6 $ $ ! " # $ & ' ( * % , - + . $ 1 6 $ $ " ! " ! ! ! 0 ! 6 3 3 6 $ $ 1 $ 1 $ 1 6 3 3 $ , ! ! ! $1 . # 6 $ $ . # 0 2 ! ! ! ! . # 6 3 3 $ 1 6 $ $ 1 6 3 3 1 $ 1 , $ - 6 $ $ 1 6 $ $ 1 $1 6 3 3 1 $1 6 2 % & 7 % . # ! ! 5$ 1 3 5 $ 1 3 $ 1 6 $ $ 1 6 $ $ 1 $ 1 6 3 3 1 $ 1 6 3 3 1 6 $ $ 1 , $ 1 3 6 3 3 1 6 $ $ 1 $ 1 6 $ $ 1 6 3 3 1 # + 6 $ $ / $ 4 # ! 3 # 3 6 3 3 1 6 3 3 1
data sheet 15 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram pin configuration and block diagrams 2.2 512 mbit ddr2 addressing table 5 512-mbit ddr2 addressing configuration 32-mbit x 16 note bank address ba[1:0] number of banks 4 auto-precharge a10 / ap row address a[12:0] column address a[9:0] number of column address bits 10 1) 1) referred to as ?colbits? number of i/os 16 2) 2) referred to as ?org? page size [bytes] 2048 (2k) 3) 3) pagesize = 2 colbits org/8 [bytes
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram pin configuration and block diagrams data sheet 16 rev. 1.31, 2006-03 05102005-c5u8-7tle 2.3 block diagrams block diagrams of the 512m ddr2 sdram component. figure 2 block diagram 8 mbit 16 i/o 4 internal memory banks note: 1. 32mb 16 organisation with 13 row, 2 bank and 10 column external adresses 2. this functional block diagram is intended to facilitate user understandin g of the operation of the device; it does not represent an actual circuit implementation. 3. ldm, udm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional ldqs and udqs signals. - 0 " 4 # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o l u m n $ e c o d e r # o n t r o l , o g i c 2 o w ! d d r e s s - 5 8 ) / ' a t i n g $ - - a s k , o g i c 2 e f r e s h # o u n t e r # o l u m n ! d d r e s s # o u n t e r , a t c h # / , ! d d r e s s 2 e g i s t e r - o d e 2 e g i s t e r s # o m m a n d $ e c o d e 2 ! 3 # ! 3 7 % # 3 # + # + # + % ! ! " ! " ! $ a t a - a s k 7 r i t e & ) & / $ r i v e r s # / , # + # + 2 e c e i v e r s ) n p u t 2 e g i s t e r - 5 8 # / , $ 1 3 ' e n e r a t o r $ r i v e r s $ a t a $ 1 3 $ 1 3 2 e a d , a t c h $ , , # + # + 5 $ 1 3 5 $ 1 3 $ 1 $ 1 / $ 4 # o n t r o l 5 $ - , $ - , $ 1 3 , $ 1 3 / $ 4 " a n k " a n k 2 o w ! d d r e s s , a t c h $ e c o d e r " a n k " a n k x " a n k " a n k " a n k - e m o r y ! r r a y x x 3 e n s e ! m p l i f i e r " a n k " a n k # o n t r o l , o g i c
data sheet 17 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3 functional description 3.1 simplified state diagram figure 3 simplified state diagram note: this simplified state diagram is intended to provide a floorplan of the possible state transitions and the commands to control them. in particul ar situations involving more than one bank, enabling / disabling on-die termination, power-down entry / exit, timing restrictions during state transitions - among other things - are not captured in full detail. - 0 & 4 ! u t o m a t i c 3 e q u e n c e # o m m a n d 3 e q u e n c e 0 r e c h a r g i n g 7 r i t i n g w i t h ! 0 0 r e c h a r g e 0 o w e r $ o w n / # $ c a l i b r a t i o n 2 e a d i n g w i t h ! 0 7 2 ! 2 $ ! 7 2 ! 2 $ ! 2 e a d 7 r i t e 0 2 0 2 ! 0 2 0 2 ! 0 2 0 2 ! 2 $ ! 2 e a d 7 r i t e 7 r i t i n g 2 e a d i n g 7 r i t e 2 e a d ! c t i v e 0 o w e r $ o w n " a n k ! c t i v e # + % , # + % ( ! c t i v a t i n g # + % , # + % , % - 2 3 3 e t t i n g - 2 3 o r % - 2 3 ! # 4 0 2 # + % , 3 e l f 2 e f r e s h 3 2 & # + % ( 2 % & # + % , 2 e f r e s h i n g # + % , ) d l e ! l l b a n k s p r e c h a r g e d # + % , # + % ( ) n i t i a l i z a t i o n 3 e q u e n c e 7 2 !
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 18 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.2 basic functionality read and write accesses to the ddr2 sdram are burst oriented; accesses star t at a selected location and continue for the burst length of four or eight in a programmed sequence. accesses begin with the registration of an activate command, which is followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. ba[1:0] selects the bank, a[12:0] selects the row for x16 components. the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto-precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following se ctions provide detailed information covering device initialization, register definition, command descript ion and device operation. 3.3 power on and initialization ddr2 sdram?s must be powered up an d initialized in a pred efined manner. operatio nal procedures other than those specified may result in undefined operation. power-up and init ialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2 v ddq and odt at a low state (all other inputs may be undefined). to guarantee odt off, v ref must be valid and a low leve l must be applied to the odt pin. maximum power up interval for v dd / v ddq is specified as 20.0 ms. the power interval is defined as the amount of time it takes for v dd / v ddq to power-up from 0 v to v ddq . at least one of these two sets of conditions must be met: ? v dd , v ddl and v ddq are driven from a single power converter output, and ? v tt is limited to v ddq max/2, and ? v ref tracks v ddq /2 or ? apply v dd before or at the same time as v ddl. ? apply v ddl before or at the same time as v ddq. ? apply v ddq before or at the same time as v tt & v ref . 2. start clock (ck, ck ) and maintain stable power and clock condition for a minimum of 200 s. 3. apply nop or deselect commands and take cke high. 4. continue nop or deselect commands for 400 ns, then issue a precharge all command. 5. issue emrs(2) command. 6. issue emrs(3) command. 7. issue emrs(1) command to enable dll. 8. issue a mrs command for ?dll reset?. 9. issue precharge-all command. 10. issue 2 or more auto-refresh commands. 11. issue the final mrs command to turn the dll on and to set the necessary operating parameter. 12. at least 200 clocks after step 8, issue emrs(1) commands to either execute the ocd calibration or select the ocd default. issue the final emrs(1) command to exit ocd calibration mode and set the necessary operating parameters. 13. the ddr2 sdram is now ready for normal operation. figure 4 initialization sequence after power up #+ #+ #+% # ommand ./0 ./0 ./0 02%!,, ./0 ./0 %-23 ./0 -23 ./0 02%!,, ./0 ./0 ./0 ./0 -23 ./0 ns t 20 t -23 t -23 t 20 t 2&# t 2&# t -23
data sheet 19 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.4 programming the m ode register and exte nded mode registers for application flexibility, bu rst length, burst type, cas latency, dll reset function , write recovery time (wr) are user defined variables and must be programmed with a mode register set (mrs) command. additionally, dll disable function, additive cas latency, driver impedance, on die termination (odt), single-ended strobe and off chip driver impedance adjustment (ocd) are also user defined variables and must be programmed with an extended mode register set (emrs) command. conten ts of the mode register (mr) or extended mode registers (emr(1, 2, 3)) can be altered by re-executing the mrs and emrs commands. if the user chooses to modify only a subset of the mr or emr variables, all variables must be redefined when the mrs or emrs commands are issued. after initial po wer up, all mrs and emrs commands must be issued before read or write cycles may begin. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. either mrs or emrs commands are activated by the low signals of cs , ras , cas and we at the positive edge of the clock.when both bank addresses ba[1:0] are 0, the ddr2 sdram enables the mrs command. when the bank address ba0 is 1 and ba1 is 0, the ddr2 sdram enables the emrs(1) command. the address input data during this cycle defines the parameters to be set as shown in the mrs and emrs tables. a new command may be issued after the mode register set command cycle time (t mrd ). mrs, emrs and dll reset do not affect array contents, which means reinstallation including those can be executed any time after power-up without af fecting array contents.
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 20 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.5 ddr2 sdram mode register set (mrs) the mode register stores the data for controlling the various operating modes of ddr2 sdram. it programs cas latency, burst length, bu rst sequence, test mode, dll reset, write recovery (wr) and various vendor specific options to make ddr2 sdram useful for various applications. the default value of the mode register is not defined, th erefore the mode register must be written after power-up for proper operation. the mode register is writte n by asserting low on cs , ras , cas , we , ba[1:0], while controlling the state of address pins a[13:0]. the ddr2 sdram should be in all bank precharged (idle) mode with cke already high prior to writing into the mode register. the mode register set command cycle time ( t mrd ) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharged state. the mode register is divided into various fields depending on functionality. burst length is defined by a[2:0] with options of 4 and 8 bit burst length. burst address sequence type is defined by a3 and cas latency is defined by a[6:4]. a7 is used for test mode and must be set to 0 for normal dram operation. a8 is used for dll reset. a[11:9] are used for write recovery time (wr) definition for auto-precharge mode. with address bit a12 two power-down modes can be selected, a ?standard mode? and a ?low-power? power- down mode, where the dll is disabled. address bit a13 and all ?higher? address bits have to be set to 0 for compatibility with other ddr2 memory products with higher memory densities.
data sheet 21 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description table 6 mode register definition (ba[2:0] = 000b) field bits type 1) description ba2 16 reg. addr. bank address [2] note: ba2 not available on 256 mbit and 512 mbit components 0 b ba2 , bank address ba1 15 bank address [1] 0 b ba1 , bank address ba0 14 bank address [0] 0 b ba0 , bank address a13 13 address bus[13] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a13 , address bit 13 pd 12 w active power-down mode select 0 b pd , fast exit 1 b pd , slow exit wr [11:9] w write recovery 2) note: all other bit comb inations are illegal. 001 b wr , 2 010 b wr , 3 011 b wr , 4 100 b wr , 5 101 b wr , 6 dll 8 w dll reset 0 b dll , no 1 b dll , yes tm 7 w test mode 0 b tm , normal mode 1 b tm , vendor specific test mode cl [6:4] w cas latency note: all other bit comb inations are illegal. 010 b cl , reserved 011 b cl , 3 100 b cl , 4 101 b cl , 5 110 b cl , 6 111 b cl , 7 - 0 " 4 " ! " ! " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 0 $ 7 2 " , r e g a d d r w w w w w w $ , , 4 - # , " 4 w
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 22 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.6 ddr2 sdram extended mode register set emr(1) the extended mode register emr(1) stores the data for enabling or disabling the dll, output driver strength, additive latency, ocd program, odt, dqs and output buffers disable, rqds and rdqs enable. the default value of the extended mode register emr(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. the extended mode register is written by asserting low on cs, ras, cas, we, ba1 and high on ba0, while controlling the state of the address pins a0 is used for dll enable or disable. a1 is used for enabling half-strength data-output driver. a2 and a6 enables on-die termination (odt) and sets the rtt value. a[5:3] are used for additive latency settings and a[9:7] enables the ocd impedance adjustment mode. a10 enables or disables the differential dqs and rdqs signals, a11 disables or enables rdqs. address bit a12 have to be set to 0 for normal operation. with a12 set to 1 the sdram outputs are disabled and in hi-z. 1 on ba0 and 0 for ba1 have to be set to access the emrs(1). a13 and all ?higher? address bits have to be se t to 0 for compatibility with other ddr2 memory products with higher memory densities. refer to extended mode register definition. bt 3 w burst type 0 b bt , sequential 1 b bt , interleaved bl [2:0] w burst length note: all other bit comb inations are illegal. 010 b bl , 4 011 b bl , 8 1) w = write only register bits 2) number of clock cycles for write reco very during auto-precharge. wr in cloc k cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wr [cycles] t wr (ns) / t ck (ns). the mode register must be programmed to fulfill the minimum requirement for the analogue t wr timing wr min is determined by t ck.max and wr max is determined by t ck.min . table 6 mode register definition (ba[2:0] = 000b) field bits type 1) description table 7 extended mode register definition (ba[2:0] = 001b) field bits type 1) description ba2 16 reg. addr. bank address [2] note: ba2 not available on 256 mbit and 512 mbit components 0 b ba2 , bank address ba1 15 bank address [1] 0 b ba1 , bank address ba0 14 bank address [0] 0 b ba0 , bank address - 0 " 4 " ! " ! " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 1 o f f 2 $ 1 3 $ 1 3 / # $ 0 r o g r a m 2 t t ! , 2 t t $ ) # $ , , r e g a d d r w w w w w w w w
data sheet 23 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description a13 13 w address bus[13] note: a13 is not available for 256 mb it and x16 512 mbit configuration 0 b a13 , address bit 13 qoff 12 output disable 0 b qoff , output buffers enabled 1 b qoff , output buffers disabled rdqs 11 read data strobe output (rdqs, rdqs) 0 b rdqs , disable 1 b rdqs , enable dqs 10 complement data st robe (dqs output) 0 b dqs , enable 1 b dqs , disable ocd program [9:7] off-chip driver calibration program 000 b ocd , ocd calibration mode exit, maintain setting 001 b ocd , drive (1) 010 b ocd , drive (0) 100 b ocd , adjust mode 111 b ocd , ocd calibration default al [5:3] additive latency note: all other bit combinations are illegal. 000 b al , 0 001 b al , 1 010 b al , 2 011 b al , 3 100 b al , 4 101 b al , 5 110 b al , 6 r tt 2,6 nominal termination resistance of odt 00 b rtt , (odt disabled) 01 b rtt , 75 ohm 10 b rtt , 150 ohm 11 b rtt , 50 ohm dic 1 off-chip driver impedance control 0 b dic , full (driver size = 100%) 1 b dic , reduced dll 0 dll enable 0 b dll , enable 1 b dll , disable 1) w = write only register bits table 7 extended mode register definition (ba[2:0] = 001b) field bits type 1) description
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 24 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.7 dll enable/disable the dll must be enabled for normal operation. dll enable is required during po wer up initialization, and upon returning to normal operation after having the dll disabled. the dll is autom atically disabled when entering self-refresh operation and is automatically re- enabled and reset upon exit of self-refresh operation. any time the dll is reset, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for syn chronization to occur may result in a violation of the t ac or t dqsck parameters. 3.8 output disable (qoff) under normal operation, the dram outputs are enabled during read operation for driving data (qoff bit in the emr(1) is set to 0). when the qoff bit is set to 1, the dram outputs will be disabled. disabling the dram outputs allows users to measure i dd currents during read operations, without including the output buffer current and external load currents. 3.9 single-ended and differen tial data strobe signals table 8 lists all possible combinations for dqs, dqs , rdqs, rqds which can be programmed by a[11:10] address bits in emrs. rdqs and rdqs are available in 8 components only. if rdqs is enabled in 8 components, the dm function is disabled. rdqs is active for reads and don?t care for writes. table 8 single-ended and differential data strobe signals emrs(1) strobe function matrix signaling a11 (rdqs enable) a10 (dqs enable) rdqs/dm rdqs dqs dqs 0 (disable) 0 (enable) dm hi-z dqs dqs differential dqs signals 0 (disable) 1 (disable) dm hi-z dq s hi-z single-ended dqs signals 1 (enable) 0 (enable) rdqs rdqs dqs dqs differential dqs signals 1 (enable) 1 (disable) rdqs hi-z dqs hi-z single-ended dqs signals
data sheet 25 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.10 extended mode register emr(2) the extended mode registers emr(2) and emr(3) are reserved for future use and must be programmed when setting the mode register during initialization.the extended mode register emr(2) is written by asserting low on cs , ras , cas , we , ba0 and high on ba1, while controlling the states of the address pins. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time ( t mrd ) must be satisfied to complete the write operation to the emr(2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. table 9 emrs(2) programming extended mode register definition (ba[2:0]=010 b ) field bits type 1) 1) w = write only description ba2 16 w bank address[2] note: ba2 is not available on 256mbit and 512mbit components 0 b ba2 , bank address ba [15:14] w bank adress[15:14] 00 b ba , mrs 01 b ba , emrs(1) 10 b ba , emrs(2) 11 b ba , emrs(3): reserved a [13:7] w address bus[13:0] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a[13:0] , address bits a7 w address bus[7] note: adapted self refresh rate for tcase > 85 c 0 b a7 , disable 1 b a7 , enable 2)3) a [6:3] w address bus[6:0] 0 b a[6:0] , address bits partial self refresh for 4 banks a [2:0] w address bus[2:0], partial array self refresh for 4 banks 000 b pasr0 , full array 001 b pasr1 , half array (ba[1:0]=00, 01) 010 b pasr2 , quarter array (ba[1:0]=00) 011 b pasr3 , not defined 100 b pasr4 , 3/4 array (ba[1:0]=01, 10, 11) 101 b pasr5 , half array (ba[1:0]=10, 11) 110 b pasr6 , quarter array (ba[1:0]=11) 111 b pasr7 , not defined %$ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ uhjdggu 65) 3$65
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 26 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.11 extended mode register emr(3) the extended mode register emr(3) is reserved for future use and all bits except ba0 and ba1 must be programmed to 0 when setting the mode register during initialization. the emrs(3) is written by asserting low on cs, ras, cas, we, ba2 and high on ba0 and ba1, while controlling the state of the address pins. 2) when dram is operated at 85c t case 95c the extended self refresh rate must be enabled by setting bit a7 to "1" before the self refresh mode can be entered. 3) if pasr (partial array self refresh) is enabled, data locate d in areas of the array beyond the specified location will be los t if self refresh is entered. data integrity will be maintained if tref conditions are met and no self refresh command is issued table 10 emr(3) programming extended mode register definition (ba[2:0]=010 b ) field bits type 1) 1) w = write only description ba2 16 w bank address[2] note: ba2 is not available on 256mbit and 512mbit components 0 b ba2 , bank address ba1 15 bank adress[1] 1 b ba1 , bank address ba0 14 bank adress[0] 1 b ba0 , bank address a[13:0]w address bus[13:0] note: a13 is not available for 256 mbit and x16 512 mbit configuration 0 b a[13:0] , address bits - 0 " 4 " ! " ! " ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! r e g a d d r
data sheet 27 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.12 off-chip driver (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart below is an example of the sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before entering ocd impedance adjustment and on die termination (odt) should be carefully controlled depending on system environment. ocd impedance adjustment flow chart figure 5 ocd impedance adjustment flow chart note: mr should be set before enter ing ocd impedance adjustment and odt should be carefully controlled depending on system environment - 0 & 4 3 t a r t % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t . e e d # a l i b r a t i o n % - 2 3 % n t e r ! d j u s t - o d e " , c o d e i n p u t t o a l l $ 1 s ) n c $ e c o r . / 0 % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t % - 2 3 $ r i v e $ 1 $ 1 3 ( i g h $ 1 3 , o w ! , , / + % - 2 3 $ r i v e $ 1 $ 1 3 , o w $ 1 3 ( i g h 4 e s t 4 e s t % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t % - 2 3 % n t e r ! d j u s t - o d e " , c o d e i n p u t t o a l l $ 1 s ) n c $ e c o r . / 0 . e e d # a l i b r a t i o n % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t % - 2 3 / # $ c a l i b r a t i o n m o d e e x i t % n d ! , , / +
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 28 rev. 1.31, 2006-03 05102005-c5u8-7tle extended mode register set for ocd impedance adjustment ocd impedance adjustment can be done using the following emrs(1) mode. in dr ive mode all outputs are driven out by ddr2 sdram and drive of rdqs is dependent on emr(1) bit enabling rdqs operation. in drive(1)mode, all dq, dq s (and rdqs) signals are driven high and all dqs (and rdqs ) signals are driven low. in drive(0) mode, all dq, dqs (and rdqs ) signals are driven low and all dqs (and rdqs) signals are driven high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver characteristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. output driver characteristics for ocd calibra tion default are specified in the following table. ocd applies only to normal full strength output drive setting defined by emr(1) and if half strength is set, ocd default driver characteristics are not applicable. when o cd calibration adjust mode is used, ocd default output driver characteristics are not applicable. after ocd ca libration is completed or driver strength is set to default, subsequent emrs(1) commands not intended to adjust ocd characteristics must specify a[9:7] as?000? in order to maintain the default or calibrated value. ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs(1) command along with a 4 bit burst code to ddr2 sdram as in the following table. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive the burst code to all dqs at the same time. dt0 in the table means all dq bits at bit time 0, dt1 at bit time 1, and so forth. the driver output impedance is adjusted for all ddr2 sdram dqs simultaneously and after ocd calibration, all dqs of a given ddr2 sdram will be adjusted to the same driver strength setting. the ma ximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. the default setting may be any step within the maximum step count range. when adjust mode command is issued, al from previously set value must be applied. for proper operation of adjust mode, wl = rl - 1 = al + cl - 1 clocks and t ds / t dh should be met as shown in figure 6 . input data pattern fo r adjustment, dt[0:3] is fixed and not affected by mrs addressing mode (i.e. sequential or interleave). burst length of 4 have to be programmed in the mrs for ocd impedance adjustment. table 11 off chip driver program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqs, ( rdqs) high and dqs (rdqs ) low 0 1 0 drive(0) dq, dqs, (rdqs) low and dqs (rdqs ) high 1 0 0 adjust mode 1 1 1 ocd calibration default table 12 off-chip-driver adjust program 4 bit burst code inputs to all dqs operation dt0 dt1 dt2 dt3 pull-up driver strength pull-down driver strength 0 0 0 0 nop (no operation) nop (no operation) 0 0 0 1 increase by 1 step nop 0 0 1 0 decrease by 1 step nop 0 1 0 0 nop increase by 1 step 1 0 0 0 nop decrease by 1 step 0 1 0 1 increase by 1 step increase by 1 step 0 1 1 0 decrease by 1 step increase by 1 step 1 0 0 1 increase by 1 step decrease by 1 step
data sheet 29 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description figure 6 timing diagram adjust mode drive mode both drive(1) and drive(0) are used for controllers to measure ddr2 sdram driver impedance before ocd impedance adjustment. in this mode, all outputs are driven out t oit after ?enter drive mode? command and all output drivers are turned-off t oit after ?ocd calibration mode exit? command. see figure 7 . figure 7 timing diagram drive mode 1 0 1 0 decrease by 1 step decrease by 1 step other combinations illegal table 12 off-chip-driver adjust program 4 bit burst code inputs to all dqs operation dt0 dt1 dt2 dt3 pull-up driver strength pull-down driver strength ./0 ./0 ./0 ./0 ./0 %-23 #-$ $1?i n ./0 t72 $13?in #+#+ 7, %-23 ./0 $- $13 / # $ a d j u s t m o d e / # $ ca l i b r a t i o n m o d e e x i t t $ 3 t $ ( $ 4 $ 4 $ 4 $ 4 ./0 ./0 ./0 ./0 %-23 #-$ $1?in ./0 $ 1 3 ? i n #+#+ %-23 %n t e r $ r i v e - o d e /# $ c a l i b r a t i o n m o d e e x i t ./0 $ 1 3 h i g h $ 1 3 l o w f o r $ r i v e $ 1 3 l o w $ 1 3 h i g h f o r $ r i v e $ 1 3 h ig h f o r $ r i v e $ 1 3 h ig h f o r $ r i v e t / ) 4 t / ) 4
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 30 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.13 on-die termination (odt) on-die terminatio n (odt) is a new feature on ddr2 components that allows a dram to turn on/off termi- nation resistance. dqs and rdqs are only terminated when enabled by emr(1). for 16 configuration odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal via the odt control pin. udqs and ldqs are terminated only when enabled in the emrs(1) by address bit a10 = 0. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resis- tance for any or all dram devices. the odt function can be used for all active and standby modes. odt is turned off and not supported in self-refresh mode. figure 8 functional representation of odt switch sw1, sw2 or sw3 are enabled by the odt pin. selection between sw1, sw2 or sw3 is determined by ?rtt (nominal)? in emrs(1 ) address bits a6 & a2. target: rval1 = rval2 = rval3 = 2 rtt the odt pin will be igno red if the extended mode register (emrs(1)) is programmed to disable odt. odt truth tables the odt truth table shows which of the input pins are terminated depending on the state of address bit a10 and a11 in the emrs(1) for the device organization ( 16). to activate termination of any of these pins, the odt function has to be enabled in the emrs(1) by address bits a6 and a2. note: x = don?t care; 0 = bit se t to low; 1 = bit set to high $ 2 ! - ) n p u t " u f f e r ) n p u t 0 i n 2 v a l 2 v a l s w s w 6 $ $ 1 6 3 3 1 2 v a l 2 v a l s w s w 6 $ $ 1 6 3 3 1 2 v a l 2 v a l s w s w 6 $ $ 1 6 3 3 1 / $ 4 ? f u n c t table 13 odt truth table input pin emrs(1) address bit a10 emrs(1) address bit a11 x16 components dq[7:0] x dq[15:8] x ldqs x ldqs 0x udqs x udqs 0x ldm x udm x
data sheet 31 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description odt timing modes depending on the operating mode asynchronous or synchronous odt timings apply. asynchronous odt timings ( t aofpd , t aonpd ) apply when the on-die dll is disabled. these modes are: ? slow exit active power down mode (with mrs bit a12 is set to ?1?) ? precharge power down mode synchronous odt timings ( t aond , t aofd , t aon , t aof ) apply for all other modes. figure 9 odt timing for active and standby (idle) modes (synchronous odt timings) note: 1. synchronous odt timings apply for active mode and standby mode with cke high and for the ?fast exit? active power down mode (mrs bit a12 set to ?0?). in all these modes the on-die dll is enabled. 2. odt turn-on time ( t aon.min ) is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max. ( t aon.max ) is when the odt resistance is fully on. both are measured from t aond . 3. odt turn off time min. ( t aof.min ) is when the device starts to turn off the od t resistance.odt turn off time max. ( t aof.max ) is when the bus is in high impedance. both are measured from t aofd . # + % $ 1 / $ 4 / $ 4 # + # + 2 t t t ! / . m i n t ! / . m a x t ! / & m a x t ! / & m i n t ! / . $ t c k t ! / & $ t c k t ) 3 t ) 3 4 4 4 4 4 4 4 4 4 t ) 3
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 32 rev. 1.31, 2006-03 05102005-c5u8-7tle figure 10 odt timing for precharge power-down and active power-down mode note: asynchronous odt timings apply for precharge po wer-down mode and ?slow exit? active power down mode (mrs bit a12 set to ?1?), where the on-die dll is disabled in this mode of operation. odt timing mode switch when entering the power down modes ?slow exit? active power down and precharge power down two additional timing parameters ( t anpd and t axpd ) define if synchronous or asynchro nous odt timings have to be applied. t ! / & 0 $ m i n #+% $1 /$4 / $ 4 #+#+ l o w 4 4 4 4 4 4 4 4 4 t )3 t )3 2 t t t ! /. 0 $ m i n t ! / & 0 $ m a x t ! / .0 $ m a x
data sheet 33 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description mode entry as long as the timing parameter t anpd.min is satisfied when odt is turned on or off before entering these power-down modes, synchronous timing parameters can be applied. if t anpd.min is not satisfied, asynchronous timing parameters apply. figure 11 odt mode entry timing diagram # + % # + # + t ! . 0 $ 4 4 4 4 4 4 4 4 t ) 3 / $ 4 / $ 4 t u r n o f f t ! . 0 $ t c k / $ 4 t u r n o f f t ! . 0 $ t c k t ! / & $ 2 4 4 / $ 4 t ) 3 2 4 4 t ) 3 / $ 4 t ! / . $ 2 4 4 t ! / . 0 $ m a x / $ 4 / $ 4 t u r n o n t ! . 0 $ t c k 3 y n c h r o n o u s t i m i n g s a p p l y 3 y n c h r o n o u s t i m i n g s a p p l y ! s y n c h r o n o u s t i m i n g s a p p l y t ! / & 0 $ m a x / $ 4 2 4 4 ! s y n c h r o n o u s t i m i n g s a p p l y / $ 4 t u r n o n t ! . 0 $ t c k t ) 3
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 34 rev. 1.31, 2006-03 05102005-c5u8-7tle mode exit as long as the timing parameter t axpd.min is satisfied when odt is turned on or off after exiting these power- down modes, synchronous timing parameters can be applied. if t axpd.min is not satisfied, asynchronous timing parameters apply. figure 12 odt mode exit timing diagram # + % t ! 8 0 $ / $4 / $ 4 t u r n o f f t ! 8 0 $ t ! 8 0 $ m i n 2 t t 2 t t t ! / . 0 $ m a x 4 4 4 4 4 4 t ) 3 3 y n c h r o n o u s t i m i n g s a p p l y 4 / $ 4 t u r n o f f t ! 8 0 $ t ! 8 0 $ m i n ! s y n c h r o n o u s t i m i n g s a p p l y / $ 4 t ! / & $ 2 t t / $ 4 t ! / & 0 $ m a x 2 t t / $ 4 t u r n o n t ! 8 0 $ t ! 8 0 $ m i n 3 y n c h r o n o u s t i m i n g s a p p l y t ! / . $ t ) 3 t ) 3 / $ 4 t ) 3 / $ 4 t ) 3 / $ 4 t u r n o n t ! 8 0 $ t ! 8 0 $ m i n ! s y n c h r o n o u s t i m i n g s a p p l y 4 # + # +
data sheet 35 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.14 bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank ad dresses ba[1:0] are used to select the desired bank. for 16 components row addresses a0 through a12 have to be applied. the bank activate command must be applied before any read or write operation c an be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write command (with or without auto- precharge) on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the t rcd.min specification, then ad ditive latency must be programmed into the device to delay the r/w command which is inte rnally issued to the device. the additive latency value must be chosen to assure t rcd.min is satisfied. additive latencies of 0, 1, 2, 3, 4 and 5 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , respectively. the minimum time interval between successive bank activate commands to the same bank is determined by t rc . the minimum time interval between bank active commands to different banks is t rrd . figure 13 bank activate command cycle t rcd = 3, al = 2, t rp = 3, t rrd = 2 ! d d r e s s . / 0 # o m m a n d 4 4 4 4 4 # o l ! d d r " a n k ! 2 o w ! d d r " a n k " # o l ! d d r " a n k " ) n t e r n a l 2 ! 3 # ! 3 d e l a y t 2 # $ m i n " a n k ! t o " a n k " d e l a y t 2 2 $ ! c t i v a t e " a n k " 2 e a d ! 0 o s t e d # ! 3 ! c t i v a t e " a n k ! 2 e a d " 0 o s t e d # ! 3 2 e a d ! " e g i n s 2 o w ! d d r " a n k ! ! d d r " a n k ! 0 r e c h a r g e " a n k ! . / 0 ! d d r " a n k " 0 r e c h a r g e " a n k " 2 o w ! d d r " a n k ! ! c t i v a t e " a n k ! t 2 0 2 o w 0 r e c h a r g e 4 i m e " a n k ! t 2 # 2 o w # y c l e 4 i m e " a n k ! 4 n 4 n 4 n 4 n ! # 4 t 2 ! 3 2 o w ! c t i v e 4 i m e " a n k ! a d d i t i v e l a t e n c y ! , # + # + t # # $
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 36 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.15 read and write co mmands and access modes after a bank has been activa ted, a read or write cycle can be executed. this is accomplished by setting ras high, cs and cas low at the clock?s rising edge. we must also be defined at this time to determine whether the access cycle is a read operation (we high) or a write operation (we lo w). the ddr2 sdram provides a wide variety of fast access modes. a single read or write command will in itiate a serial read or write operation on successive clock cycles at data rates of up to 533 mb/sec/pin for main memory. the boundary of the burst cycle is restricted to specific segments of the page length. for example, the 32 mbit 4 i/o 4 bank chip has a page length of 2048 bits (defined by ca[11, 9:0]). in case of a 4-bit burst operation (burst length = 4) the page length of 2048 is divided into 512 uniquely addressable segments (4-bits i/o each). the 4-bit burst operation will occur entirely within one of the 512 segmen ts (defined by ca[8:0]) starting with the column address supplied to the device during the read or write co mmand (ca[11, 9:0]). the second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence.in case of a 8-bit burst operation (burst length = 8) the page length of 2048 is divided into 256 uniquely addressable segments (8-bits 4 i/o each). the 8-bit burst operation will occur entire ly within one of the 256 segments (defined by ca[7 :0]) beginning with the column address supplied to the device during the read or write command (ca[11, 9:0]).a new burst access must not interrupt the previous 4 bit burst operation in case of bl = 4 setting. therefore the minimum cas to cas delay ( t ccd ) is a minimum of 2 clocks for read or write cycles.for 8 bit burst operation (bl = 8) the minimum cas to cas delay ( t ccd ) is 4 clocks for read or write cycles.burs t interruption is allowed with 8 bit burst operation. for details see chapter 3.20. figure 14 read timing example cl = 3, al = 0, rl = 3, bl = 4 . / 0 . / 0 . / 0 . / 0 . / 0 2 % ! $ ! # - $ $ 1 $ 1 3 $ 1 3 2 % ! $ " . / 0 $ o u t ! $ o u t ! $ o u t ! $ o u t ! $ o u t " $ o u t " $ o u t " $ o u t " $ o u t # $ o u t # $ o u t # $ o u t # . / 2 % ! $ # t # # $ t # # $ # + # +
data sheet 37 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.16 posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a read or write command to be issued immediately after the bank activate command (or any time during the ras to cas delay time, t rcd period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is the sum of al and the cas latency (cl). therefore if a user chooses to issue a read/write command before the t rcd.min , then al greater than 0 must be written into the emr(1). the write latency (wl) is always defined as rl - 1 (read latency -1) where read latency is defined as the sum of additive latency plus cas latency (rl=al+cl). if a user chooses to issue a read command after the t rcd.min period, the read laten cy is also defined as rl = al + cl. figure 15 activate to read timing example: read followed by a write to the same bank activate to read delay < t rcd.min : al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 4 figure 16 read to write timing example: read followed by a write to the same bank activate to read delay < t rcd.min : al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 8 ! c t i v a t e " a n k ! t 2 # $ # , ! , 2 , ! , # , 7 , 2 , 0 o s t # ! 3 # - $ $ 1 $ 1 3 $ 1 3 # + # + $o u t $ o u t $o u t $ o u t $ i n $i n $i n $ i n " a n k ! 2 e a d 7r i t e " a n k ! ! c t i v a t e " a n k ! t 2 # $ # , ! , 2 , ! , # , 7 , 2 , 0 o s t # ! 3 # - $ $ 1 $ 1 3 $ 1 3 # + # + " a n k ! 2 e a d 7 r i t e " a n k ! $i n $ i n $ i n $ i n $o u t $ o u t $ o u t $o u t $o u t $ o u t $ o u t $ o u t
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 38 rev. 1.31, 2006-03 05102005-c5u8-7tle figure 17 read to write timing example: read followed by a write to the same bank activate to read delay = t rcd.min : al = 0, cl = 3, rl = (al + cl) = 3, wl = (rl -1) = 2, bl = 4 figure 18 read to write timing example: read followed by a write to the same bank activate to read delay > t rcd.min : al = 1, cl = 3, rl = 4, wl = 3, bl = 4 figure 19 write to read timing example: writ e followed by a read to the same bank al = 2, cl = 3, rl = 5, wl = 4, t wtr = 2, bl = 4 ! c t i v a t e " a n k ! " a n k ! 7r i t e t 2 # $ # , ! , 2 , ! , # , 7 , 2 , 0 o s t # ! 3 " a n k ! # - $ $ 1 $ 1 3 $ 1 3 # + # + 2 e a d $ o u t $ o u t $ o u t $ o u t $i n $i n $ i n $ i n ! c t i v a t e " a n k ! 2 , 7 , 0 o s t # ! 3 # - $ $ 1 $ 1 3 $ 1 3 # + # + " a n k ! 2 e a d $ o u t $ o u t $ o u t $ o u t $ i n $i n $ i n $ i n 7r it e " a n k ! t 2 # $ t 2 # $ m i n ! c t i v a t e " a n k ! t 2 # $ # , ! , 7 , 2 , # - $ $ 1 $ 1 3 $ 1 3 # + # + $ o u t $o u t $ o u t $o u t $i n $ i n $i n $ i n 2 e a d " a n k ! t 7 4 2 " a n k ! 7r i t e 2 , ! , # , ! ,
data sheet 39 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.17 burst mode operation burst mode operation is used to provide a constant flow of data to memory location s (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by the addresses a[2:0] of the mr. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mr. seamless burst read or write operations are supporte d. interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. for burst interruption of a read or write burst when burst length = 8 is used, see chapter 3.21 . a burst stop command is not supported on ddr2 sdram devices. notes 1. pagesize and length is a function of i/o organization: 128mb x 4 organization (ca[ 9:0], ca11); page size = 1 kbyte; page length = 2048 64mb x 8 organization (ca[9:0]); page size = 1 kbyte; page length = 1024 32mb x 16 organization (ca[9:0]); page size = 2 kbyte; page length = 1024 2. order of burst access for sequential addressing is ?nibble-based? and therefore different from sdr or ddr components table 14 burst length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 40 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.18 read command the read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the delay from the start of the command unt il the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe output (dqs) is driven low one clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs). the al is defined by the extended mode register set (emrs(1)). figure 20 basic read timing diagram figure 21 read operation example 1 rl = 5 (al = 2, cl = 3, bl = 4) $ 1 3 $ 1 3 $ 1 $ 1 3 $ 1 3 t 2 0 2 % t $ 1 3 1 m a x t 2 0 3 4 t $ 1 3 # + t ! # $ o u t $ o u t $ o u t $ o u t # , + # , + # , + # , + t # ( t # , t # + t 1 ( $ 1 3 1 m a x t 1 ( t t , : t ( : ./0 ./0 ./0 ./0 ./0 ./0 ./0 2%!$! 4 4 4 4 4 4 4 4 4 $ ou t ! $ ou t ! $ o u t ! $ o u t ! 2 , ! , # , ./0 t$13#+ #-$ $1 " 2 e a d $13 $13 0ost#!3 #+#+
data sheet 41 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description figure 22 read operation example 2 rl = 3 (al = 0, cl = 3, bl = 8) figure 23 read followed by write example rl = 5, wl = (rl-1) = 4, bl = 4 the minimum time from the read command to the write co mmand is defined by a read-to-write turn-around time, which is bl/2 + 2 clocks. figure 24 seamless read operation example 1 rl = 5, al = 2, cl = 3, bl = 4 # - $ ./0 ./0 ./0 ./0 ./0 ./0 $ 1 g s ./0 2%!$! 4 4 4 4 4 4 4 4 4 $ o ut ! $ o u t ! $ o ut ! $ o u t ! 2, #, ./0 t$13#+ $13 $13 $ o ut ! $ o u t ! $ o ut ! $ o u t ! #+#+ ./0 0osted#!3 72)4%! ./0 ./0 ./0 ./0 ./0 2%!$! 0osted#!3 4 4 $ ou t ! $ ou t ! $ o u t ! $ ou t ! 2 , ./0 #-$ $1 4 4 4 4 4 4 4 $ i n ! $ i n ! $ i n ! $ i n ! $ 1 3 $ 1 3 7, 2 , " , #+#+ ./0 ./0 ./0 ./0 ./0 ./0 ./0 2%!$! 0ost#!3 2%!$" 0ost#!3 4 4 4 4 4 4 4 4 4 $ o ut ! $ o u t ! $ o ut ! $ o ut ! $ o u t " $ ou t " $ o u t " $ o u t " 2 , ! , # , #-$ $1 $ 1 3 $ 1 3 #+#+
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 42 rev. 1.31, 2006-03 05102005-c5u8-7tle the seamless read operation is supported by enabling a read command at every bl / 2 number of clocks. this operation is allowed regardless of same or diff erent banks as long as the banks are activated. figure 25 seamless read operation example 2 rl = 3, al = 0, cl = 3, bl = 8 (non interrupting) the seamless, non interrupting 8-bit read operation is supported by enabling a read command at every bl/2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. ./0 ./0 ./0 2%!$! 0ost#!3 4 4 4 4 4 4 4 4 4 $ o ut ! $ o u t ! $ ou t ! $o u t ! $ o u t ! $ o u t ! $ o u t ! $ o u t ! 2 , # , #-$ $1 $13 $13 2%!$" 0ost#!3 $ o u t " $ ou t " $ o ut " $ o u t " $ o ./0 ./0 ./0 ./0 . / 4 #+#+
data sheet 43 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.19 write command the write command is initiated by having cs , cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl ? 1). a data strobe signal (dqs) has to be driven low (preamble) a time t wpre prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the t dqss specification must be satisfied for write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed. when the burst has finished, any additional data supplied to the dq pi ns will be ignored. the dq signal is ignored after the burst write operation is complete. the time from th e completion of the burst write to bank precharge is named ?write recovery time? ( t wr ) and is the time needed to store the write data into the memory array. t wr is an analog timing parameter (see chapter 5 ) and is not the programmed value for wr in the mrs. figure 26 basic write timing figure 27 write operation example 1 rl = 5 (al = 2, cl = 3), wl = 4, bl = 4 $ 1 3 $ 1 3 $ 1 3 $ 1 3 t $ 1 3 ( t $ 1 3 , t 7 0 2 % 7 0 3 4 t $ i n $ i n $ i n $ i n t $ 3 t $ ( ./0 ./0 ./0 ./0 ./0 0recharge ./0 72)4%! 0ost#!3 4 4 4 4 4 4 4 4 4 7, 2 , #-$ $1 ./0 $ ) . ! $ ) . ! $ ) . ! $ ) . ! t $ 1 3 3 t72 #ompletionof the"urst7rite $ 1 3 $ 1 3 #+#+
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 44 rev. 1.31, 2006-03 05102005-c5u8-7tle figure 28 write operation example 2 rl = 3 (al = 0, cl = 3), wl = 2, bl = 4 figure 29 write followed by read example rl = 7 (al = 2, cl = 5), wl = 6, t wtr = 2, bl = 4 the minimum number of clocks from the write command to the read command is (cl - 1) +bl/2 + t wtr , where t wtr is the write-to-read turn-around time t wtr expressed in clock cycles. the t wtr is not a write recovery time ( t wr ) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. ./0 ./0 ./0 ./0 ./0 72)4%! 0ost#!3 4 4 4 4 4 4 4 4 4 7, 2 , " 7 #-$ $1 ./0 $ ) . ! $ ) . ! $ ) . ! $ ) . ! t72 #ompletionof the"urst7rite t $ 1 3 3 0recharge "ank! !ctivate t20 $13 $13 #+#+ ./0 ./0 ./0 ./0 ./0 2%!$! 0ost#!3 #-$ $1 ./0 $ ) . ! $ ) . ! $ ) . ! $ ) . ! !, #, ./0 ./0 t742 4 4 4 4 4 4 4 4 4 4 7riteto2ead#, ", t 7 4 2 $ 1 3 $ 1 3 7,2, 2, #+#+
data sheet 45 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description figure 30 seamless write operation example 1 rl = 5, wl = 4, bl = 4 the seamless write operation is supported by enablin g a write command every bl/2 number of clocks. this operation is allowed regardless of same or diff erent banks as long as the banks are activated. figure 31 seamless write operation example 2 rl = 3, wl = 2, bl = 8, non interrupting the seamless non interrupting 8-bit write operation is supported by enabling a write command at every bl/2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. ./0 ./0 ./0 ./0 ./0 ./0 ./0 $ ) . ! $ ) . ! $ ) . ! $ ) . ! 72)4%! 0ost#!3 7,2, 72)4%" 0ost#!3 $ ) . " $ ) . " $ ) . " $ ) . " 4 4 4 4 4 4 4 4 4 #-$ $1 3"2 $ 1 3 $ 1 3 #+#+ ./0 ./0 ./0 ./0 ./0 ./0 ./0 $ ) . ! $ ) . ! $ ) . ! $ ) . ! 72)4%! 0ost#!3 7,2, 72)4%" 0ost#!3 $ ) . " $ ) . " $ ) . " $ ) . " 4 4 4 4 4 4 4 4 4 #-$ $1 3"2 $ 1 3 $ 1 3 #+#+
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 46 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.20 write data mask one write data mask input (dm) for 4 and 8 components and two write data mask inputs (ldm, udm) for 16 components ar e supported on ddr2 sdram?s, consistent with the implementation on ddr sdram?s. it has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. data mask is not used during read cycles. if dm is high during a write burst coincident with the write data, the write data bit is not written to the memory. for 8 components the dm function is disabled, when rdqs / rdqs are enabled by emrs(1). figure 32 write data mask timing figure 33 write operation with data mask example rl = 3 (al = 0, cl = 3), wl = 2, t wr = 3, bl = 4 dqs, dqs dqs dqs t dqsh t dqsl t wpre w pst t dq di n di n di n di n t ds dh t dm don' t car e ./0 ./0 ./0 ./0 ./0 72)4%! 4 4 4 4 4 4 4 4 4 7, 2 , #-$ $1 ./0 t72 t $ 1 3 3 0recharge "ank! !ctivate t20 $ 1 3 $ 1 3 $- $ ) . ! $ ) . ! $ ) . ! $ ) . ! #+#+
data sheet 47 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.21 burst interruption interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. a read burst can only be interrupted by another read command. read burst interruption by a write or precharge command is prohibited. 2. a write burst can only be interrupted by another write command. write burst interruption by a read or precharge command is prohibited. 3. read burst interrupt must occur exactly two clocks after the previous read command. any other read burst interrupt timings are prohibited. 4. write burst interrupt must occur exactly two clocks after the previous write command. any other read burst interrupt timings are prohibited. 5. read or write burst interruption is allowed to any bank inside the ddr2 sdram. 6. read or write burst with auto-precharge enabled is not allowed to be interrupted. 7. read burst interruption is allowed by a read with auto-precharge command. 8. write burst interruption is allowed by a write with auto-precharge command. 9. all command timings are referenced to burst length set in the mode register. they are not referenced to the actual burst. for example, minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). minimum write to precharge timing is wl + bl/ 2 + t wr , where t wr starts with the rising clock after the un-interrupted burst end and not from the end of the actual burst end. figure 34 read interrupt timing example 1 cl = 3, al = 0, rl = 3, bl = 8 figure 35 write interrupt timing example 2 cl = 3, al = 0, wl = 2, bl = 8 ./0 ./0 ./0 ./0 ./0 ./0 2%!$! 4 4 4 4 4 4 4 4 4 #-$ $1 $13 $13 2%!$" ./0 $ ou t ! $ o ut ! $ o u t ! $ ou t ! $ o ut " $ o u t " $ o u t " $ o u t " $ o ut " $ o u t " $ o ut " $ o u t #+#+ ./0 ./0 ./0 ./0 ./0 72)4%! 4 4 4 4 4 4 4 4 4 #-$ $1 $ 1 3 $ 1 3 ./0 $ i n ! $ i n ! $ i n ! $ i n ! $ i n " $ i n " $ i n " $ i n " $ o u t " $ i n " $ i n " $ i n " 72)4%" #+#+ ./0
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 48 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.22 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is triggered when cs , ras and we are low and cas is high at the rising edge of the clock. the pre-charge command can be used to precharge each bank independently or all banks simultaneously. 3 address bits a10, ba[1:0] are used to define which bank to precharge when the command is issued. note: the bank address assignment is the same for activating and precharging a specific bank. 3.22.1 read followed by a precharge the following rules apply as long as the t rtp timing parameter - internal read to precharge command delay time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 mhz . minimum read to precharge command spacing to the same bank = al + bl/2 clocks. for the earliest possible precharge, the precharge command may be issued on the rising edge which is ?a dditive latency (al) + bl/2 clocks? after a read command, as long as the minimum t ras timing is satisfied. the term (t rtp - 2 t ck ) is 0 clocks for operating frequencies less or equal 266 mhz . the term (t rtp - 2 t ck ) is one clock for frequencies higher then 266 mhz. a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. the ras precharge time ( t rp ) has been satisfied from the clock at which the precharge begins. 2. the ras cycle time ( t rc.min ) from the previous bank activation has been satisfied. figure 36 read operation followed by precharge example 1 rl=4(al=1,cl=3), bl=4, t rtp 2cks table 15 bank selection for precharge by address bits a10 ba1 ba0 precharge bank(s) 0 0 0 bank 0 only 0 0 1 bank 1 only 0 1 0 bank 2 only 0 1 1 bank 3 only 1 don?t care don?t care all banks ./0 0recharge ./0 "ank! !ctivate ./0 ./0 2%!$! 0ost#!3 4 4 4 4 4 4 4 4 4 #-$ $1 ./0 !,",clks $ o ut ! $ o u t ! $ o ut ! $ o ut ! !, #, 2, t2!3 #, t20 $13 $13 ./0 t2# t240 #+#+
data sheet 49 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description figure 37 read operation followed by precharge example 2 rl=4(al=1,cl=3), bl=8, t rtp 2cks figure 38 read operation followed by precharge example 3 rl=5(al=2,cl=3), bl=4, t rtp 2cks ./0 ./0 ./0 2%!$! 0ost#!3 4 4 4 4 4 4 4 4 4 #-$ $1 " 2 0 ./0 !,",clks $ ou t ! $ o ut ! $ ou t ! $ ou t ! !, #, 2, t2!3 #, t20 $13 $13 ./0 t2# t240 $ ou t ! $ ou t ! $ o u t ! $ ou t ! 0recharge ./0 "ank! !ctivate f i r s t b i t p r e f e t c h s e c o n d b i t p r e f e t c h #+#+ ./0 ./0 ./0 "ank! !ctivate ./0 ./0 2%!$! 0ost#!3 4 4 4 4 4 4 4 4 4 #-$ $1 " 2 0 ./0 !,",clks $ o u t ! $ o ut ! $ ou t ! $ ou t ! !, #, 2, t2!3 #, t20 0recharge $ 1 3 $ 1 3 t2# t240 #+#+
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 50 rev. 1.31, 2006-03 05102005-c5u8-7tle figure 39 read operation followed by precharge example 4 rl=6,(al=2,cl=4),bl=4, t rtp 2cks figure 40 read operation followed by precharge example 5 rl=4,(al=0,cl=4),bl=8, t rtp > 2cks 3.22.2 write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + t wr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is know n as a write recovery time ( t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. t wr is an analog timing parameter (see chapter 5.7 ) and is not the programmed value wr in the mr. ./0 ./0 ./0 2%!$! 0ost#!3 4 4 4 4 4 4 4 4 4 #-$ $1 " 2 0 ./0 !,",clocks $ o u t ! $ ou t ! $ o u t ! $ ou t ! !, #, 2, t2!3 #, t20 0recharge ! "ank! !ctivate $13 $13 ./0 ./0 t2# t240 #+#+ ./0 ./0 ./0 2%!$! 4 4 4 4 4 4 4 4 4 #-$ $1 " 2 0 ./0 !,",clks $ ou t ! $ o ut ! $ ou t ! $ ou t ! #, 2, t2!3 t20 $ 1 3 $ 1 3 ./0 t240 $ ou t ! $ ou t ! $ o u t ! $ ou t ! 0recharge ./0 "ank! !ctivate f i r s t b i t p r e f e t c h s e c o n d b i t p r e f e t c h #+#+
data sheet 51 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description figure 41 write followed by precharge example 1 wl = (rl - 1) = 3, bl = 4, t wr =3 figure 42 write followed by precharge example 2 wl=(rl -1)=4,bl=4, t wr =3 ./0 ./0 ./0 ./0 ./0 72)4%! 0ost#!3 4 4 4 4 4 4 4 4 4 7, #-$ $1 ./0 $ ) . ! $ ) . ! $ ) . ! $ ) . ! t72 #ompletionof the"urst7rite 0recharge ! ./0 $ 1 3 $ 1 3 #+#+ ./0 ./0 ./0 ./0 ./0 72)4%! 0ost#!3 4 4 4 4 4 4 4 4 4 7 , #-$ $1 ./0 $ ) . ! $ ) . ! $ ) . ! $ ) . ! t72 #ompletionof the"urst7rite 0recharge ! ./0 $ 1 3 $ 1 3 #+#+
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 52 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.23 auto-precharge operation before a new row in an active bank can be opened, the active bank must be precha rged using either the pre- charge command or the auto-precharge function. when a read or a write command is given to the ddr2 sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto- precharge function is enabled. during auto-precharge, a read command will execut e as normal with the exception that the active ba nk will begin to precharge internally on the rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto- precharge is also implemented for write commands. the precharge operation engaged by the auto- precharge command will not begi n until the last data of the write burst sequence is properly stored in the memory array. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for random data access. the ras lockout circ uit internally delays the precharge operation until the array restore operation has been completed so that the auto-precharge command may be issued with any read or write command. 3.23.1 read with auto-precharge if a10 is 1 when a read command is issued, the read with auto-precharge func tion is engaged. the ddr2 sdram starts an auto-precharge operation on the rising edge which is (al + bl/2) cycles la ter from the read with ap command if t ras.min and t rtp are satisfied. if t ras.min is not satisfied at the edge, the start point of auto-precharge op eration will be delayed until t ras.min is satisfied. if t rtp.min is not satisfied at the edge, the start point of auto -precharge operation will be delayed until t rtp.min is satisfied. in case the internal precharge is pushed out by t rtp , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto-precharge to the next activate command becomes al + t rtp + t rp . for bl = 8 the time from read with auto-precharge to the next activate command is al + 2 + t rtp + t rp . note that ( t rtp + t rp ) has to be rounded up to the next integer value. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. the ras precharge time ( t rp ) has been satisfied from the clock at which the auto-precharge begins. 2. the ras cycle time ( t rc ) from the previous bank activation has been satisfied.
data sheet 53 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description figure 43 read with auto-precharge example 1, fo llowed by an activation to the same bank ( t rc limit) rl = 5 (al = 2, cl = 3), bl = 4, t rtp 2 cks figure 44 read with auto-precharge example 2, followed by an activation to the same bank ( t ras limit) rl = 5 (al = 2, cl = 3), bl = 4, t rtp 2 cks ./0 ./0 ./0 ./0 "ank !ctivate ./0 2%!$w!0 0osted#!3 4 4 4 4 4 4 4 4 4 $ o u t ! $ o u t ! $ o u t ! $ ou t ! 2 , ! , # , ./0 #-$ $1 ! h i g h t 2 0 !uto 0recharge"egins $ 1 3 $ 1 3 t 2 ! 3 t 2 # mi n ./0 ! , " , #+#+ ./0 ./0 ./0 ./0 "ank !ctivate ./0 2%!$w!0 0osted#!3 4 4 4 4 4 4 4 4 4 $ ou t ! $ o u t ! $ o ut ! $ o u t ! 2 , ! , # , ./0 #-$ $1 ! h i g h t 2 0 !uto 0recharge"egins $ 1 3 $ 1 3 t 2 # t 2 ! 3 m i n ./0 #+#+
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 54 rev. 1.31, 2006-03 05102005-c5u8-7tle figure 45 read with auto-precharge example 3, followed by an activation to the same bank rl = 4 (al = 1, cl = 3), bl = 8, t rtp 2 cks figure 46 read with auto-precharge example 4, followed by an activation to the same bank, rl = 5 (al = 1, cl = 4), bl = 4, t rtp = 3 cks ./0 ./0 ./0 ./0 "ank !ctivate ./0 2%!$w!0 0osted#!3 4 4 4 4 4 4 4 4 4 $ o ut ! $ o ut ! $ o ut ! $ o u t ! 2 , ! , # , ./0 #-$ $1 " 2 ! 0 ! h i g h t 2 0 !uto 0recharge"egins $13 $13 ./0 $ o ut ! $ o u t ! $ ou t ! $ o u t ! f i r s t b i t p r e f e t c h s e c o nd b i t p r e f e t c h t 2 4 0 ! , " , #+#+ . / 0 . / 0 . / 0 . / 0 " a n k ! c t i v a t e . / 0 2 % ! $ w ! 0 0 o s t e d # ! 3 4 4 4 4 4 4 4 4 $ o u t ! $ o u t ! $ o u t ! $ o u t ! 2 , ! , # , . / 0 # - $ $ 1 " 2 ! 0 ! h i g h ! u t o 0 r e c h a r g e " e g i n s $ 1 3 $ 1 3 . / 0 f i r s t b i t p r e f e t c h t 2 4 0 ! , t 2 4 0 t 2 0 t 2 0 # + # + 4
data sheet 55 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.23.2 write with auto-precharge if a10 is high when a write command is issued, the write with auto-precharge function is engaged. the ddr2 sdram automatica lly begins precharge operation after the completion of the write burst plus the write recovery time delay (wr), programmed in the mrs register, as long as t ras is satisfied. the bank undergoing auto-precharge from the completion of the write burst may be reacti vated if the following two conditions are satisfied. 1. the last data-in to bank activate delay time ( t dal = wr + t rp ) has been satisfied. 2. the ras cycle time ( t rc ) from the previous bank activation has been satisfied. in ddr2 sdram?s the write recovery time delay (wr) has to be programmed into the mrs mode register. as long as the analog t wr timing parameter is not violated, wr can be programmed between 2 and 6 clock cycles. minimum write to activate command spacing to the same bank = wl + bl/2 + t dal . figure 47 write with auto-precharge example 1 ( t rc limit) wl = 2, t dal = 6 (wr = 3, t rp = 3), bl = 4 figure 48 write with auto-precharge example 2 (wr + t rp limit) wl = 4, t dal = 6 (wr = 3, t rp = 3), bl = 4 ./0 ./0 ./0 ./0 ./0 "ank! !ctivate ./0 72)4% w!0 4 4 4 4 4 4 4 4 ./0 #-$ $1 ! h i g h t 2 0 !uto 0recharge"egins $ ) . ! $ ) . ! $ ) . ! $ ) . ! 7, 2 , 72 t 2 # m i n $ 1 3 $ 1 3 # o mp l e t i o n o f t h e " u r s t 7 r i t e t $ ! , t 2 ! 3 m i n #+#+ ./0 ./0 ./0 ./0 ./0 "ank! !ctivate ./0 72)4%w!0 0osted#!3 4 4 4 4 4 4 4 ./0 #-$ $1 ! h i g h t 2 0 !uto 0recharge"egins $ ) . ! $ ) . ! $ ) . ! $ ) . ! 7, 2 , 72 t 2 # 4 4 # o m p l e t i o n o f t h e " u r st 7r i t e $ 1 3 $ 1 3 t $ ! , t 2 ! 3 #+#+
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 56 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.23.3 read or write to pr echarge command spacing summary the following table summarizes the minimum command de lays between read, read w/ ap, write, write w/ap to the precharge commands to the same banks and precharge-all commands. table 16 minimum command delays from command to command mi nimum delay between ?from command? to ?to command? unit note read precharge (to same banks as read) al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) 1) ru{ t rtp (ns) / t ck (ns)} must be used, where ru stands for ?round up? 2) for a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge-all, issued to that bank. the precharge period is satisfied after t rp,all depending on the latest precharge command issued to that bank precharge-all al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) read w/ap precharge (to same banks as read w/ap) al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) precharge-all al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) write precharge (to same banks as write) wl + bl/2 + t wr t ck 2) precharge-all wl + bl/2 + t wr t ck 2) write w/ap precharge (to same banks as write w/ap) wl + bl/2 + wr t ck 2) precharge-all wl + bl/2 + wr t ck 2) precharge precharge (to same banks as precharge) 1 t ck 2) precharge-all 1 t ck 2) precharge-all precharge 1 t ck 2) precharge-all 1 t ck 2)
data sheet 57 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.23.4 concurrent auto-precharge ddr2 devices support the ?concurrent auto- precharge? feature. a read with auto-precharge enabled, or a write with auto-precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between read data and write data must be avoided externally and on the internal data bus). the minimum delay from a read or write command with auto-precharge enabled, to a command to a different bank, is summarized in the command delay table. as defined, the wl = rl - 1 for ddr2 devices which allows the command gap and corresponding data gaps to be minimized. 3.24 refresh ddr2 sdram requires a refresh of all rows in any rolling 64 ms interval. the necessa ry refresh can be generated in one of two ways: by explicit auto-refresh commands or by an internally timed self-refresh mode. 3.24.1 auto-refresh command auto-refresh is used during normal operation of the ddr2 sdram?s. this command is non persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto-refresh command. the ddr2 sdram requires auto-refresh cycles at an average periodic interval of t refi.max . when cs , ras and cas are held low and we high at the rising edge of the cloc k, the chip enters the auto- refresh mode. all banks of the sdram must be precharged and idle for a minimum of the precharge time ( t rp ) before the auto-refresh command can be applied. an internal address counter supplies the addresses during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharge d (idle) state. a delay between the auto-refresh command and the next activate command or subsequent auto-refresh command must be greater than or equal to the auto- refresh cycle time ( t rfc ). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 t refi . table 17 command delay table from command to command (different bank, non-interrupting command) minimum delay with concurrent auto- precharge support unit note write w/ap read or read w/ap (cl -1) + (bl/2) + t wtr t ck write or write w/ap bl/2 t ck precharge or activate 1 t ck 1) 1) this rule only applies to a selective precharge comm and to another bank, a precharge-all command is illegal read w/ap read or read w/ap bl/2 t ck write or write w/ap bl/2 + 2 t ck precharge or activate 1 t ck 1)
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 58 rev. 1.31, 2006-03 05102005-c5u8-7tle figure 49 auto refresh timing 3.24.2 self-refresh command the self-refresh command can be used to retain data, even if the rest of the system is powered down. when in the self-refresh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built-in timer to accommodate self- refresh operation. the self-refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. the device must be in idle state and odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs(1) command. once the command is registered, cke must be held low to keep the device in self-refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self-refresh mode all of the external control signals, except cke, are ?don?t care?. the dram initiates a minimum of one auto refresh command internally within t cke period once it enters self refresh mode. the clock is internally disabled during self-refresh operation to save power. the minimum time that the ddr2 sdram must remain in self refresh mode is t cke . the user may change the external clock frequency or halt the external clock one clock after self-refresh en try is registered, however, the clock must be restarted and stable before the device can exit self -refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock must be stable prior to cke going back h igh. once self-refresh exit command is registered, a delay of at least t xsnr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self-refresh exit period t xsrd for proper operation. upon exit from self refresh, the ddr2 sdram can be put back into self refresh mode after t xsnr expires. nop or deselect commands must be registered on each positive clock edge during the self-refresh exit interval t xsnr . odt should be turned off during t xsnr . the use of self refresh mo de introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, the ddr2 sdram requires a minimum of one extra auto refresh command before it is put back into self refresh mode. 4 4 4 4 # + # + # - $ 0recharge t 20 ./0 !54/ 2%&2%3( !.9 ./0 t 2&# t 2&# !54/ 2%&2%3( ./0 ./0 ./0 # + % h i g h
data sheet 59 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description figure 50 self refresh timing note: 1. device must be in the ?all banks idle? state before entering self refresh mode. 2. t xsrd ( 200 t ck ) has to be satisfied for a read or a read with auto-precharge command. 3. t xsnr has to be satisfied for any command except a read or a read with auto-precharge command 4. since cke is an sstl input, v ref must be maintained during self refresh. 3.25 power-down power-down is synchronously entered when cke is registered low, along with nop or deselect command. cke is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. cke is allowed to go low while any other operation such as row activation, precharge, auto-precharge or auto-refresh is in progress, but power-down i dd specification will not be applied until finishing those operations. the dll should be in a locked state when power-down is entered. otherwise dll should be reset after exiting power-down mode for proper read operation. dram design guarantees it?s dll in a locked state with any cke intensive operations as long as dram controller complies with dram specifications. if power-down occurs when all banks are precharged, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. for active power-down two different power saving modes can be selected within the mrs register, address bit a12. when a12 is set to low this mode is referred as ?standard active power-down mode? and a fast power-down exit timing defined by the t xard timing parameter can be used. when a12 is set to high this mode is referred as a power saving ?low power active power-down mode?. this mode takes longer to exit from the power-down mode and the t xards timing parameter has to be satisfied. entering power-down deactivates the input and output buffers, excluding ck, ck , odt and cke. also the dll is disabled upon entering precharge power-down or slow exit active power-d own, but the dll is kept enabled during fast exit active power-down. in power- down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are ?don?t care?. power-down duration is limited by 9 times t refi of the device. # + # + 4 4 4 # + # + ma y b e h a l t e d # + # + mu s t b e s t a b l e # + % t 8 3 2 $ t 8 3 . 2 4 n 4 r 4 m 4 4 t 2 0
t i s t ! / & $ # - $ 3elf2efresh %ntry ./0 .on 2ead #ommand 2ead #ommand 4 t i s t i s / $ 4 t # + %
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 60 rev. 1.31, 2006-03 05102005-c5u8-7tle power-down entry active power-down mode can be entered after an activate command. precharge power-down mode can be entered after a precharge, precharge-all or internal precharge command. it is also allowed to enter power- down mode after an auto-refresh command or mrs / emrs(1) command when t mrd is satisfied. active power-down mode entry is prohibited as long as a read burst is in progress, meaning cke should be kept high until the burst operation is finished. therefore active power-down mode entry after a read or read with auto-precharge command is allowed after rl + bl/2 is satisfied. active power-down mode entry is prohibited as long as a write burst and the intern al write recovery is in progress. in case of a write command, active power- down mode entry is allowed when wl + bl/2 + t wtr is satisfied. in case of a write command with auto-precharge, power-down mode entry is allowed after the internal precharge command has been executed, which is wl + bl/2 + wr starting from the write with auto- precharge command. in this case the ddr2 sdram enters the precharge power-down mode. power-down exit the power-down state is synchronously exited when cke is registered high (alo ng with a nop or deselect command). a valid, executable command can be applied with power-down exit latency, t xp , t xard or t xards , after cke goes high. power-down exit latencies are defined in chapter 7.2. figure 51 active power-down mode entry and exit after an activate command note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. ./0 ./0 !ctivate 4 4 4 #-$ ./0 4 n 4 n #+% ! c t i v e 0 o w e r $ o w n % n t r y ./0 ./0 ! c t 0 $ t ) 3 4 n t ) 3 ! c t i v e 0 o w e r $ o w n % x i t 6alid #ommand t 8 ! 2 $ o r t 8 ! 2 $ 3
#+#+
data sheet 61 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description figure 52 active power-down mode entry and exit example after a read command rl = 4 (al = 1, cl =3), bl = 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. figure 53 active power-down mode entry and exit example after a write command wl = 2, t wtr =2,bl= 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. ./0 ./0 2%!$ 4 4 4 4 4 4 4 4 4 $ o ut ! $ o u t! $ o ut ! $ o ut ! 2 , #, #-$ $1 $13 $13 ./0 ./0 ./0 ./0 ./0 ./0 4 n 4 n #+% ! , ! ct i v e 0 o w e r $ o w n % n t r y 2 , " , ./0 ./0 ! c t 0 $ t ) 3 4 n t ) 3 ! ct i v e 0 o w e r $ o w n % xi t 6alid #ommand t 8 ! 2 $ o r t 8 ! 2 $ 3
#+#+ 2%!$w!0 ./0 ./0 72)4% 4 4 4 4 4 4 4 4 #-$ $1 $ 1 3 $ 1 3 ./0 ./0 ./0 ./0 ./0 ./0 4 n 4 n #+% 7, 2 , 7, " , t 74 2 ./0 ./0 ! c t 0 $ t 74 2 t ) 3 4 n t ) 3 6al id #ommand ! c t i v e 0 o w e r $ o w n % x it t 8 ! 2 $ o r t 8 ! 2 $ 3
#+#+ $) . ! $ ) . ! $ ) . ! $ ) . ! ! ct i v e 0 o w e r $ o w n % n t ry
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 62 rev. 1.31, 2006-03 05102005-c5u8-7tle figure 54 active power-down mode entry and exit example after a write command with ap wl = 2, wr = 3, bl = 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. wr is th e programmed value in the mrs mode register. figure 55 precharge power down mode entry and exit note: "precharge" may be an external command or an internal precharge following write with ap. figure 56 auto-refresh command to power-down entry ./0 ./0 72)4% w!0 4 4 4 4 4 4 4 4 #-$ $1 $ 1 3 $ 1 3 ./0 ./0 ./0 ./0 ./0 ./0 4 n 4 n #+% 7, 2 , 7, " , 72 ./0 ./0 ! c t 0 $ 72 t ) 3 4 n t ) 3 6ali d #ommand ! c t iv e 0 o w e r $ o w n % x i t t 8 ! 2 $ o r t 8 ! 2 $ 3
#+#+ $ ) . ! $ ) . ! $ ) . ! $ ) . ! ! c t i v e 0 o w e r $ o w n % n t r y t 8 0 ./0 ./0 0recharge
4 4 4 #-$ ./0 ./0 4 n 4 n #+% 0 r e c h a r g e 0 o w e r $ o w n % n t r y ./0 ./0 t ) 3 4 n t ) 3 0 r e c h a r g e 0 o w e r $ o w n % x i t 6alid #ommand t 2 0 ./0 4 #+#+ 4 4 4 4 4 4 n #-$ #+% #+#+ ! u t o 2 e f r e s h t 2 & # t i s t 8 0 6 a l i d # o m ma n d
data sheet 63 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description figure 57 mrs, emrs command to power-down entry 4 4 4 4 4 4 4 4 #-$ #+% #+#+ - 2 3 o r % - 2 3 t - 2 $ % n t e r s 0 r e c h a r g e 0 o w e r $ o w n -o d e
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 64 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.26 other commands 3.26.1 no operation command the no operation command (nop) should be used in cases when the sdram is in a idle or a wait state. the purpose of the no operation command is to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will no t terminate a previous operation that is still executin g, such as a burst read or write cycle. 3.26.2 deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don?t care. 3.27 input clock frequency change during operation the dram input clock frequency can be changed under the following conditions: ? during self-refresh operation ? dram is in precharge power-down mode and odt is completely turned off. in the precharge power-down mode the ddr2- sdram has to be in precharged power-down mode and idle. odt must be already turned off and cke must be at a logic low state. after a minimum of two clock cycles after t rp and t aofd have been satisfied the input clock frequency can be changed. a stable new clock frequency has to be provided, before cke can be changed to a high logic level again. after t xp has been satisfied a dll reset command via emrs(1) has to be issued. during the following dll re-lock period of 200 clock cycles, odt must remain off. after the dll- re-lock period the dram is ready to operate with the new clock frequency. figure 58 input frequency change example during precharge power-down mode ./0 ./0 4 4 4 4 4 4 x 4 x 4 y ./0 ./0 ./0 ./0 ./0 $,, 2%3%4 4 y 4 y & r e q u e n c y # h a n g e o c c u r s h e r e ./0 ./0 4 z t 8 0 3 t a b l e n e w c l o c k b e f o r e p o we r d o w n e x i t t 2 0 t ! / & $ -i n i m u m c l o c k s r e q u i r e d b e f o r e c h a n g i n g t h e f r e q u e n c y 4 y ./0 6al id #omman d c lo c k s / $ 4 i s o f f d u r i n g $ , , 2 % 3 % 4
data sheet 65 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description 3.28 asynchronous ck e low reset event in a given system, asynch ronous reset event can occur at any time without prior knowledge. in this situation, memory controlle r is forced to drop cke asynchronously low, imme diately interrupting any valid operation. dram requ ires cke to be maintained high for all valid operations as defined in this data sheet. if cke asynchronously drops low during any valid operation, the dram is not guaranteed to preserve the contents of the memory array. if this event occurs, the memory controller must satisfy a time delay ( t delay ) before turning off the clocks. stable clocks must exist at the input of dram before cke is raised high again. the dram must be fully re-initialized as described the initialization sequence (power on and initialization, step 4 through 13). dram is ready for normal operation after the initialization sequence. see chapter 7 for t delay specification. figure 59 asynchronous low reset event #+% # + % d r o p s l o w d u e t o a n a s y n c h r o n o u s r e s e t e v en t # l o c k s c a n b e t ur n e d o f f a f t e r t h i s p o in t t d el a y #+#+ s t a b l e c l o c k s
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram functional description data sheet 66 rev. 1.31, 2006-03 05102005-c5u8-7tle 3.29 dll off mode for very low frequency operations between 50 mhz and 250 mhz the dll off mode is supported. entering this mode requires an extended mode register set command disabling the dll by setting a0 to 1. for 250 mhz clock speed and faster dll on mode operation is recommended. most of the commands and timings described in chapter 3 are also applicable for dll off mode. differences exist for the frequency range, the initialization and the timing of wr command and rd command. 3.29.1 dll off frequency definition table 18 dll off frequency definition speed grade symbol ?20 ?22 ?25 ?28 ?33 unit parameter min. max. min. max. min. max. min. max. min. max. ? clock frequency @ cl = 6 t ck 50 250 50 250 50 250 50 250 50 250 mhz
data sheet 67 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram truth tables 4 truth tables table 19 command truth table function cke cs ras cas we ba0 ba1 a[13:11] a10 a[9:0] note 1)2)3) 1) the state of odt does not affect the stat es described in this table. the odt functi on is not available during self refresh. 2) ?x? means ?h or l (but a defined logic level)?. 3) operation that is not specified is ill egal and after such an event, in order to guarantee proper operat ion, the dram must be powered down and then restarted through the specified initialization sequence before no rmal operation can continue. previous cycle current cycle (extended) mode register set h h l l l l ba op code 4)5) 4) all ddr2 sdram commands are defined by states of cs , we , ras , cas , and cke at the rising edge of the clock. 5) bank addresses ba[1:0] determine which bank is to be ope rated upon. for (e)mrs ba[1:0] selects an (extended) mode register. auto-refresh h h l l l h x x x x 4) self-refresh entry h l l l l h x x x x 4)6) 6) v ref must be maintained during self refresh operation. self-refresh exit l h h x x x x x x x 4)6)7) 7) self refresh exit is asynchronous. lh h h single bank precharge h h l l h l ba x l x 4)5) precharge all banks h h l l h l x x h x 4) bank activate h h l l h h ba row address 4)5) write h h l h l l ba column l column 4)5)8) 8) burst reads or writes at bl = 4 cannot be terminated. see chapter 3.21 for details. write with auto- precharge h h l h l l ba column h column 4)5)8) read h h l h l h ba column l column 4)5)8) read with auto- precharge h h l h l h ba column h column 4)5)8) no operation h x l h h h x x x x 4) device deselect h x h x x x x x x x 4) power down entry h l h x x x x x x x 4)9) 9) the power down mode does not perform any refresh operations . the duration of power down is therefore limited by the refresh requirements outlined in chapter 3.28 lh h h power down exit l h h x x x x x x x 4)9) lh h h
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram truth tables data sheet 68 rev. 1.31, 2006-03 05102005-c5u8-7tle table 20 clock enable (cke) truth table for synchronous transitions current state 1) 1) current state is the state of the ddr2 sdram immediately prior to clock edge n. cke command (n) 2)3) ras, cas, we, cs 2) command (n) is the command registered at clock edge n, and action (n) is a result of command (n) 3) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. see chapter 3.13 . action (n) 2) note 4)5) 4) cke must be maintained high while the device is in ocd calibration mode. 5) operation that is not specified is ill egal and after such an event, in order to guarantee proper operat ion, the dram must be powered down and then restarted through the specified initialization sequence before no rmal operation can continue. previous cycle 6) (n-1) 6) cke (n) is the logic state of cke at clock edge n; cke (n-1) was the stat e of cke at the previous clock edge. current cycle 6) (n) power-down l l x maintain power-down 7)8)11) 7) the power-down mode does not perform any refresh operations . the duration of power-down mode is therefor limited by the refresh requirements 8) ?x? means ?don?t care (including floating around v ref )? in self refresh and power down. however odt must be driven high or low in power down if t he odt function is enabled (bit a2 or a6 set to ?1? in emrs(1)). l h deselect or nop power-down exit 7)9)10)11) 9) all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 10) valid commands for po wer-down entry and exit are nop and deselect only. 11) t cke.min of 3 clocks means cke must be registered on three consec utive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid leve l during the time period of t is + 2 t cke + t ih . self refresh l l x main tain self refresh 8)11)12) 12) v ref must be maintained during self refresh operation. l h deselect or nop self refresh exit 9)12)13)14) 13) on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the txsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 14) valid commands for self refr esh exit are nop and deselct only. bank(s) active h l deselect or nop active power-down entry 7)9)10)11)15) 15) power-down and self refresh can not be entered while read or write operations , (extended) mode register operations, precharge or refresh operations are in progress. see chapter 3.25 and chapter 3.24.2 for a detailed list of restrictions. all banks idle h l deselect or nop precharge power-down entry 9)10)11)15) h l autorefresh self refresh entry 7)11)14)16) 16) self refresh mode can only be enter ed from the all banks idle state. any state other than listed above h h refer to the command truth table 17) 17) must be a legal command as defined in the command truth table. table 21 data mask (dm) truth table name (function) dm dqs note write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit h x 1)
data sheet 69 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics 5 electrical characteristics 5.1 absolute maximum ratings table 22 dram component operating temperature range symbol parameter rating unit notes t case operating temperature 0 to 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dr am specification will be s upported. during operation, the dram case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s. 4) when operating this product in the 85c to 95c t case temperature range, the high temperature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. note, when the high te mperature self refresh is enabled there is an increase of i dd6 by approximately 50% table 23 absolute maximum ratings symbol parameter rating unit notes min max v dd voltage on v dd pin relative to v ss ?1.0 2.3 v 1) 1) stresses greater than those listed under ?absolute maximum ratings? may ca use permanent damage to the device. this is a stress rating only and functional opera tion of the device at these or any other conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. v ddq voltage on v ddq pin relative to v ss ?0.5 2.3 v 1) v ddl voltage on vddl pin relative to v ss ?0.5 2.3 v 1) v in , v out voltage on any pin relative to v ss ?0.5 2.3 v 1) t j junction temperature 125 c 1) t stg storage temperature ?55 150 c 1)2) 2) storage temperature is the case surface te mperature on the center/top side of the dram.
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics data sheet 70 rev. 1.31, 2006-03 05102005-c5u8-7tle 5.2 dc characteristics table 24 recommended dc operating conditions (sstl_18) symbol parameter rating unit notes min. typ. max. v dd supply voltage 1.7 1.8 1.9 v 1)2) 1) hyb18t512161bf?[25/28/33] 2) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v dddl supply voltage for dll 1.7 1.8 1.9 v 1)2) v ddq supply voltage for output 1.7 1.8 1.9 v 1)2) v dd supply voltage 1.9 2.0 2.1 v 2)3) 3) hyb18t512161bf?[20/22] v dddl supply voltage for dll 1.9 2.0 2.1 v 2)3) v ddq supply voltage for output 1.9 2.0 2.1 v 2)3) v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4)5) 4) the value of v ref may be selected by the user to provide optimum noise margin in the system. typicall y the value of v ref is expected to be about 0.5 v ddq of the transmitting device and v ref is expected to track variations in v ddq . 5) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 6) 6) v tt is not applied directly to the device. v tt is a system supply for signal terminatio n resistors, is expected to be set equal to v ref , and must track variations in die dc level of v ref . table 25 odt dc electrical characteristics parameter / cond ition symbol min. nom. max. unit note termination resistor impedance value for emrs(1)[a6,a2] = [0,1]; 75 ohm rtt1(eff) 60 75 90 ? 1) 1) measurement definition for rtt(eff): apply v ih(ac) and v il(ac) to test pin separately, then measure current i(v ihac ) and i(v ilac ) respectively. rtt(eff) = (v ih(ac) ? v il(ac) ) /(i(v ihac ) ? i(v ilac )). termination resistor impedance value for emrs(1)[a6,a2] =[1,0]; 150 ohm rtt2(eff) 120 150 180 ? 1) termination resistor impedance value for emrs(1)(a6,a2)=[1,1]; 50 ohm rtt3(eff) 40 50 60 ? 1) deviation of v m with respect to v ddq / 2 delta v m ?6.00 ? + 6.00 % 2) 2) measurement definition for v m : turn odt on and measure voltage (v m ) at test pin (midpoint) with no load: delta v m = ((2 x v m /v ddq )?1)x100% table 26 input and output leakage currents symbol parameter / cond ition min. max. unit notes iil input leakage current; any input 0 v < v in < v dd ?2 +2 a 1) 1) all other pins not under test = 0 v iol output leakage current; 0 v < vout < v ddq ?5 +5 a 2) 2) dq?s, ldqs, ldqs , udqs, udqs , dqs, dqs , rdqs, rdqs are disabled and odt is turned off
data sheet 71 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics 5.3 dc & ac characteristics ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) ?enable dqs ? mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or fa lling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is verified by design and char acterization but not subject to production test. in single ended mode, the dqs (and rdqs ) signals are internally disabled and don?t care. figure 60 single-ended ac input test conditions diagram table 27 dc & ac logic input levels symbol parameter min. max. units v ih(dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il(dc) dc input low ?0.3 v ref ? 0.125 v v ih(ac) ac input logic high v ref + 0.250 ? v v il(ac) ac input low ? v ref ? 0.250 v table 28 single-ended ac input test conditions symbol condition value unit notes v ref input reference voltage 0.5 x v ddq v 1) 1) input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. v swing.max input signal maximum peak to peak swing 1.0 v 1) slew input signal minimum slew rate 1.0 v / ns 2)3) 2) the input signal minimum slew rate is to be maintained over the range from v ih(ac).min to v ref for rising edges and the range from v ref to v il(ac).max for falling edges as shown in figure 60 3) ac timings are referenced with input waveforms switching from v il(ac) to v ih(ac) on the positive transitions and v ih(ac) to v il(ac) on the negative transitions. table 29 differential dc and ac input and output logic levels symbol parameter min. max. unit notes v in(dc) dc input signal voltage ?0.3 v ddq + 0.3 ? 1) v id(dc) dc differential input voltage 0.25 v ddq + 0.6 ? 2) 6 $ $ 1 6 ) ( a c m i n 6 ) ( d c m i n 6 2 % & 6 ) , d c m a x 6 ) , a c m a x 6 3 3 6 3 7) . ' - ! 8 d e l t a 4 2 d e l t a 4 & 6 ) , a c m a x d e l t a 4 & & a l l i n g 3 l e w 2 i s i n g 3 l e w 6 ) ( a c m i n d e l t a 4 2 6 2 % & 6 2 % &
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics data sheet 72 rev. 1.31, 2006-03 05102005-c5u8-7tle figure 61 differential dc and ac input and output logic levels diagram 5.4 output buffer characteristics v id(ac) ac differential input voltage 0.5 v ddq + 0.6 v 3) v ix(ac) ac differential cross point input voltage 0.5 v ddq ? 0.175 0.5 v ddq + 0.175 v 4) v ox(ac) ac differential cross point output voltage 0.5 v ddq ? 0.125 0.5 v ddq + 0.125 v 5) 1) v in(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs etc. 2) v id(dc) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(dc) ? v il(dc) . 3) v id(ac) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(ac) ? v il(ac) . 4) the value of v ix(ac) is expected to equal 0.5 v ddq of the transmitting device and v ix(ac) is expected to track variations in v ddq . v ix(ac) indicates the voltage at which diff erential input signals must cross. 5) the value of v ox(ac) is expected to equal 0.5 v ddq of the transmitting device and v ox(ac) is expected to track variations in v ddq . v ox(ac) indicates the voltage at which diff erential input signals must cross. table 30 full strength calibrated pull-up driv er characteristics voltage (v) calibrated pull-up driver current [ma] nominal minimum 1) (21 ohms) 1) the driver characteristics evaluation conditions are nominal minimum 95 c ( t case ). v ddq = 1.7 v, any process nominal low 2) (18.75 ohms) 2) the driver characteristics evaluation cond itions are nominal low and nominal high 25 c ( t case ), v ddq = 1.8 v, any process nominal (18 ohms) 3) 3) the driver characteristics evaluation conditions are nominal 25 c ( t case ), v ddq = 1.8 v, typical process nominal high 2) (17.25 ohms) nominal maximum 4) (15 ohms) 4) the driver characteristics evaluation conditions are nominal maximum 0 c ( t case ), v ddq = 1.9 v, any process 0.2 ?9.5 ?10.7 ?11.4 ?11.8 ?13.3 0.3 ?14.3 ?16.0 ?16.5 ?17.4 ?20.0 0.4 ?18.3 ?21.0 ?21.2 ?23.0 ?27.0 table 29 differential dc and ac input and output logic levels symbol parameter min. max. unit notes # r o s s i n g 0 o i n t 6 $ $ 1 6 3 3 1 6 ) $ 6 ) 8 o r 6 / 8 6 4 2 6 # 0
data sheet 73 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics table 31 full strength calibrated pu ll-down driver characteristics voltage (v) calibrated pull-down driver current [ma] nominal minimum 1) (21 ohms) 1) the driver characteristics evaluation conditions are nominal minimum 95 c ( t case ). v ddq = 1.7 v, any process nominal low 2) (18.75 ohms) 2) the driver characteristics evaluation cond itions are nominal low and nominal high 25 c ( t case ), v ddq = 1.8v, any process nominal 3) (18 ohms) 3) the driver characteristics evaluation conditions are nominal 25 c ( t case ), v ddq = 1.8 v, typical process nominal high 2) (17.25 ohms) nominal maximum 4) (15 ohms) 4) the driver characteristics evaluation conditions are nominal maximum 0 c ( t case ), v ddq = 1.9 v, any process 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics data sheet 74 rev. 1.31, 2006-03 05102005-c5u8-7tle 5.5 input / output capacitance table 32 input / output capacitance symbol parameter min. max. unit cck input capacitance, ck and ck 1.0 2.0 pf cdck input capacitance delta, ck and ck ?0.25 pf ci input capacitance, all other input-only pins 1.0 1.75 pf cdi input capacitance delta, a ll other input-only pins ? 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs , rdqs, rdqs 2.5 3.5 pf cdio input/output capacitance delta, dq, dm, dqs, dqs , rdqs, rdqs ?0.5 pf
data sheet 75 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics 5.6 overshoot and unde rshoot specification figure 62 ac overshoot / undershoot diagram for address and control pins figure 63 ac overshoot / undershoot diagram for clock, data, strobe and mask pins table 33 ac overshoot / undershoot specification for address and control pins parameter ?20 ?22 ?25 ?28 ?33 unit maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 0.5 0.5 v maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 0.5 0.5 v maximum overshoot area above v dd 0.80 0.80 0.80 0.80 0.80 v.ns maximum undershoot area below v ss 0.80 0.80 0.80 0.80 0.80 v.ns table 34 ac overshoot / undershoot specification for clock, data, strobe and mask pins parameter ?20 ?22 ?25 ?28 ?33 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 0.9 0.9 v maximum overshoot area above v ddq 0.23 0.23 0.23 0.23 0.23 v.ns maximum undershoot area below v ssq 0.23 0.23 0.23 0.23 0.23 v.ns 6 $ $ 6 3 3 / v e r s h o o t ! r e a 5 n d e r s h o o t ! r e a - a x i m u m ! m p l i t u d e - a x i m u m ! m p l i t u d e 4 i m e n s 6 o l t s 6 6 $ $ 1 6 3 3 1 / v e r s h o o t ! r e a 5 n d e r s h o o t ! r e a - a x i m u m ! m p l i t u d e - a x i m u m ! m p l i t u d e 4 i m e n s 6 o l t s 6
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics data sheet 76 rev. 1.31, 2006-03 05102005-c5u8-7tle 5.7 ac characteristics 5.7.1 speed grade definitions table 35 speed grade definition speed grade ?20 ?22 ?25 ?28 ?33 unit note parameter symbol min. max. min. m ax. min. max. min. max. min. max. clock frequency @ cl = 3 t ck 3.75 8 3.75 8 3.75 8 3.75 8 3.75 8 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 8timings ar e further guaranteed for normal ocd dr ive strength (emrs(1) a1 = 0) under the ?reference load for timing measurements? according to chapter 8.1 only. 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoi nt when in differential strobe mode; the input reference level for signals other than ck/ck, dqs / dqs, rdqs / rdqs is defined in chapter 8.3. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . see section 8 for the reference load for timing measurements. @ cl = 4 t ck 3.75 8 3.75 8 3.75 8 3.75 8 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 38 38 38 38 3.338 ns 1)2)3)4) @ cl = 6 t ck 2.58 2.58 2.58 2.88 3.338 ns 1)2)3)4) @ cl = 7 t ck 2.08 2.28 ?? ?? ?? ns 1)2)3)4) row active time t ras 45k 70k 45k 70k 45k 70k 45k 70k 45k 70k ns 1)2)3)4) 5) 5) t ras.max is calculated from the maximum amount of time a ddr 2 device can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60? 60? 60? 60? 60? ns 1)2)3)4) ras-cas-delay t rcd 15? 15? 15? 15? 15? ns 1)2)3)4) row precharge time t rp 15? 15? 15? 15? 15? ns 1)2)3)4)
data sheet 77 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics 5.7.2 ac timing parameters list of timing parameters table 36 timing parameter by speed grade parameter symbol ?20 ?22 ?25 unit notes 1)2)3)4) 5)6) min. max. min. max. min. max. dq output access time from ck / ck t ac ?450 +450 ?450 +450 ?500 +500 ps cas a to cas b command period t ccd 2?2?2? t ck ck, ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck cke minimum high and low pulse width t cke 3?3?3? t ck ck, ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck auto-precharge wr ite recovery + precharge time t dal wr + t rp ?wr+ t rp ?wr+ t rp ? t ck 7)18) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? t is + t ck + t ih ?? t is + t ck + t ih ?? ns 8) dq and dm input hold time (differential data strobe) t dh 270 ?? 345 ?? 375 ?? ps 9) dq and dm input hold time (single ended data strobe) t dh1 270 ?? 345 ?? 375 ?? ps 9) dq and dm input pulse width (each input) t dipw 0.35 ? 0.35 ? 0.35 ? t ck dqs output access time from ck / ck t dqsck ?450 + 450 ?450 + 450 ?500 + 500 ps 9) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 450 ? 450 ? 450 ps 10) write command to 1st dqs latching transition t dqss wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 t ck dq and dm input setup time (differential data strobe) t ds 345 345 ?? 375 ?? ps 9) dq and dm input setup time (single ended data strobe) t ds1 270 345 ?? 375 ?? ps 9) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? 0.2 ? t ck clock half period t hp min. ( t cl, t ch )min. ( t cl, t ch )min. ( t cl, t ch ) 11) data-out high-impedance time from ck / ck t hz ? t ac.max ? t ac.max ? t ac.max ps 12)
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics data sheet 78 rev. 1.31, 2006-03 05102005-c5u8-7tle address and control input hold time t ih 650 650 ? 700 ? ps address and control input pulse width (each input) t ipw 0.6 ? 0.6 ? 0.6 ? t ck address and control input setup time t is 650 650 ? 700 ? ps dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max 2 t ac.min t ac.max 2 t ac.min t ac.max ps 12) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max t ac.min t ac.max t ac.min t ac.max ps 12) mode register set command cycle time t mrd 2?2?2? t ck ocd drive mode output delay t oit 012012012 ns data output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ? t hp ? t qhs ? data hold skew factor t qhs ? 600 ? 600 ? 600 ps average periodic refresh interval t refi ? 7.8 ? 7.8 ? 7.8 s 13)14) ? 3.9 ? 3.9 ? 3.9 s 13)15) auto-refresh to active/auto- refresh command period t rfc 105 ? 105 ? 105 ? ns 16) read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck 12) read postamble t rpst 0.40 0.60 0.40 0.60 0.40 0.60 t ck 12) active bank a to active bank b command period t rrd 10 ? 10 ? 10 ? ns 14)17) internal read to precharge command delay t rtp 7.5 ? 7.5 ? 7.5 ? ns write preamble t wpre 0.35 x t ck ? 0.35 x t ck ? 0.35 x t ck ? t ck write postamble t wpst 0.40 0.60 0.40 0.60 0.40 0.60 t ck 17) write recovery time for write without auto-precharge t wr 13 ? 13 ? 15 ? ns write recovery time for write with auto-precharge wr t wr / t ck t wr / t ck t wr / t ck t ck 18) internal write to read command delay t wtr 7.5 ? 7.5 ? 7.5 ? ns 19) exit power down to any valid command (other than nop or deselect) t xard 2?2?2? t ck 20) exit active power-down mode to read command (slow exit, lower power) t xards 10 ? al ? 9 ? al ? 8 ? al ? t ck 20) table 36 timing parameter by speed grade parameter symbol ?20 ?22 ?25 unit notes 1)2)3)4) 5)6) min. max. min. max. min. max.
data sheet 79 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2?2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? t rfc +10 ? t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? 200 ? 200 ? t ck 1) v ddq , v dd refer to chapter 1 . 2) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 5 of this data sheet. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs / dqs , rdqs / rdqs is defined in chapter 5.3 of this data sheet. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . see chapter 5 for the reference load for timing measurements. 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr para meter stored in the mr. 8) the clock frequency is allowed to change during self-refr esh mode or precharge power-down mode. in case of clock frequency change during power-down, a specific procedure is required as described in chapter 3.27 . 9) timing is referenced to vref-crossing; minimal slewrate at input pin should be 3v/ns 10) consists of data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the sa me access time windows as valid data transitions.these parameters ar e verified by design and characterizati on, but not subject to production test. 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 14)0 c t case 85 c 15) 85 c < t case 95 c 16) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 17) the maximum limit for the t wpst parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turn around) degrades accordingly. 18) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 19) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 20) user can choose two different active power-down modes for additional power saving via mrs address bit a12. in ?standard active power-down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. table 36 timing parameter by speed grade parameter symbol ?20 ?22 ?25 unit notes 1)2)3)4) 5)6) min. max. min. max. min. max.
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics data sheet 80 rev. 1.31, 2006-03 05102005-c5u8-7tle table 37 timing parameter by speed grade parameter symbol ?28 ?33 unit notes 1)2)3)4) 5)6) min. max. min. max. dq output access time from ck / ck t ac ?550 +550 ?600 +600 ps cas a to cas b command period t ccd 2?2? t ck ck, ck high-level width t ch 0.45 0.55 0.45 0.55 t ck cke minimum high and low pulse width t cke 3?3? t ck ck, ck low-level width t cl 0.45 0.55 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ?wr+ t rp ? t ck 7)18) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? t is + t ck + t ih ?? ns 8) dq and dm input hold ti me (differe ntial data strobe) t dh 400 ?? 420 ?? ps 9) dq and dm input hold time (single ended data strobe) t dh1 400 ?? 420 ?? ps 9) dq and dm input pulse width (each input) t dipw 0.35 ? 0.35 ? t ck dqs output access time from ck / ck t dqsck ?550 + 550 ?600 + 600 ps 9) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck dqs-dq skew (for dq s & associated dq signals) t dqsq ?450?450 ps 10) write command to 1st dqs latching transition t dqss wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 t ck dq and dm input setu p time (differential data strobe) t ds 400 ?? 420 ?? ps 9) dq and dm input setup time (single ended data strobe) t ds1 400 ?? 420 ?? ps 9) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck clock half period t hp min. ( t cl, t ch )min. ( t cl, t ch ) 11) data-out high-impedance time from ck / ck t hz ? t ac.max ? t ac.max ps 12) address and control input hold time t ih 750 ? 800 ? ps address and control input pulse width (each input) t ipw 0.6 ? 0.6 ? t ck address and control input setup time t is 750 ? 800 ? ps dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max 2 t ac.min t ac.max ps 12) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max t ac.min t ac.max ps 12) mode register set command cycle time t mrd 2?2? t ck ocd drive mode output delay t oit 012012 ns data output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ?
data sheet 81 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics data hold skew factor t qhs ?600?600 ps average periodic refresh interval t refi ?7.8?7.8 s 13)14) ?3.9?3.9 s 13)15) auto-refresh to ac tive/auto-refresh command period t rfc 105 ? 105 ? ns 16) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 12) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 12) active bank a to active bank b command period t rrd 10 ? 10 ? ns 14)17) internal read to precharge command delay t rtp 7.5 ? 7.5 ? ns write preamble t wpre 0.35 x t ck ?0.35 x t ck ? t ck write postamble t wpst 0.40 0.60 0.40 0.60 t ck 17) write recovery time for write without auto- precharge t wr 15 ? 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck t wr / t ck t ck 18) internal write to read command delay t wtr 7.5 ? 7.5 ? ns 19) exit power down to any valid command (other than nop or deselect) t xard 2?2? t ck 20) exit active power-down mode to read command (slow exit, lower power) t xards 7 ? al ? 6 ? al ? t ck 20) exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? 200 ? t ck 1) v ddq , v dd refer to chapter 1 . 2) timing that is not specified is illegal and after such an ev ent, in order to guarantee pro per operation, the dram must be powered down and then restarted through the specified init ialization sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 5 of this data sheet. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs / dqs , rdqs / rdqs is defined in chapter 5.3 of this data sheet. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . see chapter 5 for the reference load for timing measurements. 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr para meter stored in the mr. 8) the clock frequency is allowed to change during self-refr esh mode or precharge power-down mode. in case of clock frequency change during power-down, a specific procedure is required as described in chapter 3.27 . 9) timing is referenced to vref-crossing; minimal slewrate at input pin should be 3v/ns 10) consists of data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. table 37 timing parameter by speed grade parameter symbol ?28 ?33 unit notes 1)2)3)4) 5)6) min. max. min. max.
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics data sheet 82 rev. 1.31, 2006-03 05102005-c5u8-7tle 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and t he actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific volta ge level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid data transitions.these parameters ar e verified by design and characterizati on, but not subject to production test. 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 14) 0 c t case 85 c 15) 85 c < t case 95 c 16) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 17) the maximum limit for the t wpst parameter is not a device limit. the device ope rates with a greater va lue for this parameter, but system performance (bus turn around) degrades accordingly. 18) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 19) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 20) user can choose two different active power-down modes for ad ditional power saving via mrs address bit a12. in ?standard active power-down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied.
data sheet 83 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram electrical characteristics 5.7.3 odt ac electri cal characteristics table 38 odt ac electrical characteristics and operating conditions for all bins symbol parameter / condition unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max +0.7ns ns 1) 1) odt turn on time min. is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max +1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max +0.6ns ns 2) 2) odt turn off time min. is when the device starts to turn o ff odt resistance. odt turn off ti me max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max +1ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram specifications and conditions data sheet 84 rev. 1.31, 2006-03 05102005-c5u8-7tle 6 specifications and conditions table 39 i dd measurement conditions parameter symbol note operating current - one bank active - precharge t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , cke is high, cs is high between valid commands. address and control inputs are switching; databus in puts are switching. i dd0 1)2)3)4) 5)6) operating current - one bank active - read - precharge i out = 0 ma, bl = 4, t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , t rcd = t rcd(idd) , al = 0, cl = cl(idd); cke is high, cs is high between valid commands. address and control inputs are switching; databus inputs are switching. i dd1 1)2)3)4) 5)6) precharge power-down current all banks idle; cke is low; t ck = t ck(idd) ;other control and address inputs are stable; data bus inputs are floating . i dd2p 1)2)3)4) 5)6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are switching, data bus inputs are switching . i dd2n 1)2)3)4) 5)6) precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are stable, data bus inputs are floating. i dd2q 1)2)3)4) 5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit). i dd3p(0) 1)2)3)4) 5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to 1 (slow power-down exit); i dd3p(1) 1)2)3)4) 5)6) active standby current all banks open; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switch ing; data bus inputs are switching; i dd3n 1)2)3)4) 5)6) operating current burst read: all banks open; continuous bu rst reads; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max.(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r 1)2)3)4) 5)6) operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w 1)2)3)4) 5)6) burst refresh current t ck = t ck(idd) , refresh command every t rfc = t rfc(idd) interval, cke is high, cs is high between valid commands, other control and address inputs are switching, data bu s inputs are switching. i dd5b 1)2)3)4) 5)6) distributed refresh current t ck = t ck(idd) , refresh command every t refi = 7.8 s interval, cke is low and cs is high between valid commands, other control and addre ss inputs are switching, data bus inputs are switching. i dd5d 1)2)3)4) 5)6)
data sheet 85 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram specifications and conditions self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. i dd6 1)2)3)4) 5)6) operating bank interleave read current 1. all banks interleaving reads, i out = 0 ma; bl = 4, cl = cl (idd) , al = t rcd(idd) -1 t ck(idd) ; t ck = t ck(idd) , t rc = t rc(idd) , t rrd = t rrd(idd) ; cke is high, cs is high between valid commands. address bus inputs are stable during deselects; data bus is switching. i dd7 1)2)3)4) 5)6)7) 1) v ddq = 2.0 v 0.1 v; v dd = 2.0 v 0.1 v 2) i dd specifications are tested after the device is properly initialized. 3) i dd parameter are specified with odt disabled. 4) data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs and udqs . 5) definitions for i dd : see table 40 6) timing parameter minimum and maximum values for i dd current measurements are defined in chapter 7.. 7) a = activate, ra = read wi th auto-precharge, d=deselect table 40 definition for i dd parameter description low defined as v in v il(ac).max high defined as v in v ih(ac).min stable defined as inputs are stable at a high or low level floating defined as inputs are v ref = v ddq / 2 switching defined as: inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for dq signals not including mask or strobes table 39 i dd measurement conditions parameter symbol note
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram specifications and conditions data sheet 86 rev. 1.31, 2006-03 05102005-c5u8-7tle table 41 i dd specification speed grade ?20 ?22 ?25 -28 -33 unit note symbol typ. typ. typ. typ. typ. i dd0 92 87 81 77 70 ma 16 i dd1 99 94 89 85 78 ma 16 i dd2p 44444ma i dd2n 46 43 41 38 33 ma i dd2q 40 38 38 35 31 ma i dd3p(0) 30 29 28 27 23 ma 1) 1) mrs(12)=0 i dd3p(1) 55554ma 2) 2) mrs(12)=1 i dd3n 52 48 47 43 37 ma i dd4r 166 158 153 145 127 ma 16 i dd4w 189 173 163 149 129 ma 16 i dd5b 127 122 119 115 109 ma i dd5d 55554ma 3) 3) 0 t case 85c i dd6 44443ma 3) i dd7 204 204 193 193 179 ma 16
data sheet 87 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram specifications and conditions 6.1 i dd test conditions for testing the i dd parameters, the following timing parameters are used: table 42 i dd measurement test condition parameter symbol ?20 ?22 ?25 ?28 ?33 unit notes cas latency cl idd 77666t ck clock cycle time t ckidd 2.5 2.5 2.5 2.5 2.5 ns active to read or write delay t rcd.idd 15 15 15 15 15 ns active to active / auto -refresh command period t rc.idd 60 60 60 60 60 ns active bank a to active bank b command delay t rrd.idd 10 10 10 10 10 ns 1) 1) 16 (2 kb page size) precharge command period t ras.min.idd 45k 45k 45k 45k 45k ns precharge command period t ras.max.idd 70k 70k 70k 70k 70k ns precharge command period t ras.max.idd 15 15 15 15 15 ns auto-refresh to active / auto-refresh command period t rp.idd 105 105 105 105 105 ns average periodic refresh interval 0 c t case 85 c t rfc.idd 7.8 7.8 7.8 7.8 7.8 s 85 c t case 95 c t refi 3.9 3.9 3.9 3.9 3.9 s
hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram specifications and conditions data sheet 88 rev. 1.31, 2006-03 05102005-c5u8-7tle 6.1.1 on die termination (odt) current the odt function adds additional current consumption to the ddr2 sd ram when enabled by the emrs(1). depending on address bits a6 & a2 in the emrs(1) a ?wea k? or ?strong? termination can be selected. the current consumption for any terminated input pin depends on whether the input pin is in tri-state or driving ?0? or ?1?, as long a odt is enabled during a given period of time.. see table 43 note: for power consumption calculations the odt duty cycle has to be taken into account table 43 odt current per terminated input pin odt current emrs(1) state min. typ. max. unit enabled odt current per dq added i ddq current for odt enabled; odt is high; data bus inputs are floating i odto a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0 2.5 3 3.75 ma/dq a6 = 1, a2 = 1 7.5 9 11.25 ma/dq active odt current per dq added i ddq current for odt enabled; odt is high; worst case of data bus inputs are stable or switching. i odtt a6 = 0, a2 = 1 10 12 15 ma/dq a6 = 1, a2 = 0 5 6 7.5 ma/dq a6 = 1, a2 = 1 15 18 22.5 ma/dq
data sheet 89 rev. 1.31, 2006-03 05102005-c5u8-7tle hyb18t512161bf?20/22/25/28/33 512-mbit double-data -rate-two sdram package 7 package 7.1 package dimension figure 64 package outline p-tfbga-84 (top view) 7.2 package thermal characteristics table 44 package thermal characteristics jesd51 theta_ja 1) 1) junction to ambient thermal resistance. the value has been obtained by simulation using t he conditions stated in the jedec jesd-51 standard. theta_jc 2) 2) junction to case thermal resistance. the value has been obtained by simulation. jedec board 1s0p 2s0p air flow 0 m/s 1 m/s 3 m/s 0 m/s 1 m/s 3 m/s rth[k/w] 69 53 47 41 35 33 5
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